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Writes reg(31) on x31 when running on the board

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This commit is contained in:
Julien THILLARD
2025-11-09 19:47:05 +01:00
parent 441f665d34
commit 15d9707571
1 changed files with 8 additions and 6 deletions
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14
src/main/scala/projet/RegFile.scala
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@@ -34,12 +34,14 @@ class RegFile(sim: Boolean = false) extends Module {
// Simulation stuff // Simulation stuff
if (sim) { if (sim) {
io.valid_x31.get := false.B io.valid_x31.get := false.B
} io.x31 := "hDEADC0DE".U
io.x31 := "hDEADC0DE".U when(io.we && io.rd_addr === 31.U) {
when(io.we && io.rd_addr === 31.U) { io.x31 := io.rd_data
io.x31 := io.rd_data if (sim) {
if (sim) { io.valid_x31.get := true.B
io.valid_x31.get := true.B }
} }
} else {
io.x31 := regs(31.U)
} }
} }