Implements stage 5

src/main/scala/projet/ControlUnit.scala

@@ -8,32 +8,52 @@ class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
     val reg_file_we = Output(Bool())
     val alu_opcode = Output(AluOpCode())
+    val optype = Output(OpType())
 
-    val mux_imm_alu = Output(Bool())
+    val mux_alu_imm = Output(Bool())
+    val mux_rega_pc = Output(Bool())
 }
 
-object OPCode extends ChiselEnum {
+object OpType extends ChiselEnum {
+    val U, I = Value
+}
+
+object OpCode extends ChiselEnum {
     val LUI = 0b0110111.U
     val AUIPC = 0b0010111.U
+    val ADDI = 0b0010011.U
 }
 
 class ControlUnit() extends Module {
-    import OPCode._
+    import OpCode._
 
     val io = IO(new CUInterface())
 
     io.reg_file_we := false.B
     io.alu_opcode := AluOpCode.Add
-    io.mux_imm_alu := false.B;
+    io.optype := OpType.U
+    io.mux_alu_imm := true.B;
+    io.mux_rega_pc := true.B;
     switch(io.instruction(6, 0)) {
+
+        // U instructions
         is(LUI) {
             io.reg_file_we := true.B
-            io.mux_imm_alu := false.B;
+            io.mux_alu_imm := false.B
+            io.optype := OpType.U
         }
         is(AUIPC) {
             io.alu_opcode := AluOpCode.Add 
             io.reg_file_we := true.B
-            io.mux_imm_alu := true.B;
+            io.mux_rega_pc := false.B
+            io.optype := OpType.U
+        }
+
+        // I instructions
+        is(ADDI) {
+            io.alu_opcode := AluOpCode.Add 
+            io.reg_file_we := true.B
+            io.optype := OpType.I
         }
     }
 }