43 lines
1.5 KiB
Markdown
43 lines
1.5 KiB
Markdown
This repository contains a podman image whichs contains all necessary tools to generate and flash bitstream file from a SystemVerilog program.
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It is build for the xilinx zybo zynq7 `xc7z010` card, but it can probably be easily edited to support another card.
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# Installation
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You will need [podman](https://podman.io/) to run the image.
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## Use the pre-built image
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You can directly use the pre-build image present in the repo
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```bash
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zstd -d fmn.tar.zst
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podman load --input fmn.tar
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```
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## Build the image from source
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You can build the image yourself by using this command:
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```bash
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podman build -t fmn_alpine .
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```
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It will first create an image which will build every tools, and then create the final image containing only needed binaries and libraries.
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For information, it takes around 5.63GB space and 10 minutes to build on my device.
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# Tools
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- [sv2v](https://github.com/zachjs/sv2v) : Convert SystemVerilog to Verilog.
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- [yosys](https://github.com/YosysHQ/yosys) : Do RTL synthesis from verilog files.
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- [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) : placing and routing tool.
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- [fasm2frames](https://github.com/f4pga/prjxray) : Convert fasm files to frames files.
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- [xc7frames2bit](https://github.com/f4pga/prjxray) : Convert frames files to bitstream.
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- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flash a bitstream on a FPGA card.
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The image also contains some [databases](https://github.com/f4pga/prjxray-db) needed for prjxray tools to work.
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# Usage
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See the small [example](./example/).
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