1.5 KiB
1.5 KiB
This repository contains a podman image whichs contains all necessary tools to generate and flash bitstream file from a SystemVerilog program.
It is build for the xilinx zybo zynq7 xc7z010 card, but it can probably be easily edited to support another card.
Installation
You will need podman to run the image.
Use the pre-built image
You can directly use the pre-build image present in the repo
zstd -d fmn.tar.zst
podman load --input fmn.tar
Build the image from source
You can build the image yourself by using this command:
podman build -t fmn_alpine .
It will first create an image which will build every tools, and then create the final image containing only needed binaries and libraries.
For information, it takes around 5.63GB space and 10 minutes to build on my device.
Tools
- sv2v : Convert SystemVerilog to Verilog.
- yosys : Do RTL synthesis from verilog files.
- nextpnr-himbaechel : placing and routing tool.
- fasm2frames : Convert fasm files to frames files.
- xc7frames2bit : Convert frames files to bitstream.
- openFPGALoader : Flash a bitstream on a FPGA card.
The image also contains some databases needed for prjxray tools to work.
Usage
See the small example.