mwa/bisare_sim_rs
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Implemented correct behavior for lsl, asr, lsr (mask and correct for input = 32)

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Mwa
2026-03-19 21:35:49 +01:00
parent c844f8d806
commit c72e133cde
1 changed files with 3 additions and 3 deletions
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6
simu/src/cpu.rs
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@@ -449,15 +449,15 @@ impl Computer {
self.pc += 1; self.pc += 1;
} }
Instruction::Lsl(reg, reg1, op2) => { Instruction::Lsl(reg, reg1, op2) => {
self[reg] = self[reg1] << self.resolve(op2); self[reg] = (self[reg1] as u64).wrapping_shl(self.resolve(op2)) as u32;
self.pc += 1; self.pc += 1;
} }
Instruction::Lsr(reg, reg1, op2) => { Instruction::Lsr(reg, reg1, op2) => {
self[reg] = self[reg1] >> self.resolve(op2); self[reg] = (self[reg1] as u64).wrapping_shr(self.resolve(op2)) as u32;
self.pc += 1; self.pc += 1;
} }
Instruction::Asr(reg, reg1, op2) => { Instruction::Asr(reg, reg1, op2) => {
self[reg] = (self[reg1] as i32 >> self.resolve(op2)) as u32; self[reg] = (self[reg1] as i64).wrapping_shr(self.resolve(op2)) as u32;
self.pc += 1; self.pc += 1;
} }
Instruction::Umull(reg, reg1, op2) => { Instruction::Umull(reg, reg1, op2) => {