diff --git a/simu/src/cpu.rs b/simu/src/cpu.rs
index 9594f20..b8ecc3a 100644
--- a/simu/src/cpu.rs
+++ b/simu/src/cpu.rs
@@ -449,15 +449,15 @@ impl Computer {
                         self.pc += 1;
                     }
                     Instruction::Lsl(reg, reg1, op2) => {
-                        self[reg] = self[reg1] << self.resolve(op2);
+                        self[reg] = (self[reg1] as u64).wrapping_shl(self.resolve(op2)) as u32;
                         self.pc += 1;
                     }
                     Instruction::Lsr(reg, reg1, op2) => {
-                        self[reg] = self[reg1] >> self.resolve(op2);
+                        self[reg] = (self[reg1] as u64).wrapping_shr(self.resolve(op2)) as u32;
                         self.pc += 1;
                     }
                     Instruction::Asr(reg, reg1, op2) => {
-                        self[reg] = (self[reg1] as i32 >> self.resolve(op2)) as u32;
+                        self[reg] = (self[reg1] as i64).wrapping_shr(self.resolve(op2)) as u32;
                         self.pc += 1;
                     }
                     Instruction::Umull(reg, reg1, op2) => {