mwa/bisare_sim_rs
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minor performance improvement for jump/call

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This commit is contained in:
Mwa
2026-03-20 11:18:48 +01:00
parent ff6427b020
commit b5962c6b50
1 changed files with 8 additions and 11 deletions
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19
simu/src/cpu.rs
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@@ -163,7 +163,6 @@ impl TryFrom<u32> for Instruction {
Ok(match value >> 30 {
0b00 => {
let t = value & (1 << 29); // 3rd bit set
let value = value - t;
let t = t != 0;
if t {
Self::Call(value)
@@ -589,10 +588,8 @@ impl Computer {
self.pc += d as usize
}
}
Instruction::Jump(mut addr) => {
if addr & (1 << 28) != 0 {
addr += 7 << 29;
} else if addr == 0 {
Instruction::Jump(addr) => {
if unlikely(addr == 0) {
#[cfg(feature = "debug")]
{
match self.interupts {
@@ -616,15 +613,14 @@ impl Computer {
}
SHARED.external_interupts.wait(0);
}
self.pc = (addr + self.pc as u32) as usize;
self.pc = ((addr + self.pc as u32) & 0x1FFF_FFFF) as usize;
}
Instruction::Call(mut addr) => {
Instruction::Call(addr) => {
//WARNING! addr still has the type bit set at this point!
self.sp -= 1;
self.ram[self.sp] = ((self.pc << 2) + 4) as u32;
if addr & (1 << 28) != 0 {
addr += 7 << 29;
} else if unlikely(addr == 0) {
if unlikely(addr == 0 + (1 << 29) /*t bit*/) {
#[cfg(feature = "debug")]
{
println!("program terminated");
@@ -634,7 +630,8 @@ impl Computer {
#[cfg(not(feature = "debug"))]
exit(0);
}
self.pc = (addr + self.pc as u32) as usize;
//The mask take care of both wrapping and shedding the t bit
self.pc = ((addr + self.pc as u32) & 0x1FFF_FFFF) as usize;
}
Instruction::Ret() => {
self.pc = (self.ram[self.sp] >> 2) as usize;