mwa/bisare_sim_rs
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

improved debug

Browse Source
This commit is contained in:
Mwa
2026-03-27 22:40:28 +01:00
parent 689f4b77fd
commit 128a53bd3b
1 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
simu/src/main.rs
View File

@@ -399,14 +399,14 @@ fn debug_loop(com: &mut Computer) {
Commands::Run { desigantor } => match desigantor {
Some(s) => match parse_int::parse::<usize>(s.as_str()) {
Ok(addr) => {
while com.pc != (addr / 4) {
while com.pc != (addr / 4) && !com.error {
com.debug_step(1);
}
debug_context(com);
}
Err(_) => match com.book.1.get(s.as_str()).cloned() {
Some(addr) => {
while com.pc != (addr as usize / 4) {
while com.pc != (addr as usize / 4) && !com.error {
com.debug_step(1);
}
debug_context(com);
@@ -425,9 +425,9 @@ fn debug_loop(com: &mut Computer) {
},
Commands::Up => {
let curr_sp = com.sp;
while (com.sp < curr_sp)
|| ((com.ram[com.pc] != (0b10001000 << 24))
&& (com.ram[com.pc] != (0b10101000 << 24)))
while (com.sp < curr_sp
|| (com.ram[com.pc] != (0b10001000 << 24) && com.ram[com.pc] != (0b10101000 << 24)))
&& !com.error
{
com.debug_step(1);
}