mwa/bisare_sim_rs
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improved debug

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This commit is contained in:
Mwa
2026-03-27 22:40:28 +01:00
parent 689f4b77fd
commit 128a53bd3b
1 changed files with 5 additions and 5 deletions
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10
simu/src/main.rs
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@@ -399,14 +399,14 @@ fn debug_loop(com: &mut Computer) {
Commands::Run { desigantor } => match desigantor { Commands::Run { desigantor } => match desigantor {
Some(s) => match parse_int::parse::<usize>(s.as_str()) { Some(s) => match parse_int::parse::<usize>(s.as_str()) {
Ok(addr) => { Ok(addr) => {
while com.pc != (addr / 4) { while com.pc != (addr / 4) && !com.error {
com.debug_step(1); com.debug_step(1);
} }
debug_context(com); debug_context(com);
} }
Err(_) => match com.book.1.get(s.as_str()).cloned() { Err(_) => match com.book.1.get(s.as_str()).cloned() {
Some(addr) => { Some(addr) => {
while com.pc != (addr as usize / 4) { while com.pc != (addr as usize / 4) && !com.error {
com.debug_step(1); com.debug_step(1);
} }
debug_context(com); debug_context(com);
@@ -425,9 +425,9 @@ fn debug_loop(com: &mut Computer) {
}, },
Commands::Up => { Commands::Up => {
let curr_sp = com.sp; let curr_sp = com.sp;
while (com.sp < curr_sp) while (com.sp < curr_sp
|| ((com.ram[com.pc] != (0b10001000 << 24)) || (com.ram[com.pc] != (0b10001000 << 24) && com.ram[com.pc] != (0b10101000 << 24)))
&& (com.ram[com.pc] != (0b10101000 << 24))) && !com.error
{ {
com.debug_step(1); com.debug_step(1);
} }