247 lines
8.4 KiB
Rust
247 lines
8.4 KiB
Rust
use crate::println;
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// Configuration pour RISC-V Virt
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const PCI_ECAM_BASE: usize = 0x3000_0000;
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const VIRTIO_VENDOR_ID: u16 = 0x1af4;
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#[derive(Debug, Default, Clone, Copy)]
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pub struct VirtioPciRegion {
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pub bar_address: usize,
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pub offset: u32,
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pub length: u32,
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}
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// Helpers ECAM
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fn pci_read<T>(bus: u8, dev: u8, func: u8, offset: u16) -> T {
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let addr = PCI_ECAM_BASE
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| ((bus as usize) << 20)
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| ((dev as usize) << 15)
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| ((func as usize) << 12)
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| (offset as usize);
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unsafe { core::ptr::read_volatile(addr as *const T) }
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}
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fn pci_write<T>(bus: u8, dev: u8, func: u8, offset: u16, val: T) {
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let addr = PCI_ECAM_BASE
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| ((bus as usize) << 20)
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| ((dev as usize) << 15)
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| ((func as usize) << 12)
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| (offset as usize);
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unsafe { core::ptr::write_volatile(addr as *mut T, val) }
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}
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#[derive(Copy, Clone, Debug)]
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pub struct VirtioPciCaps {
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pub common_cfg: usize,
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pub notify_cfg: usize,
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pub isr_cfg: usize,
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pub notify_multiplier: u32,
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}
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#[derive(Debug, Clone, Copy)]
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pub struct PciDevice {
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pub bus: u8,
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pub device: u8,
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}
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pub struct PciGeneralDevice(PciDevice);
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impl PciDevice {
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pub fn new(bus: u8, device: u8) -> Self {
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Self { bus, device }
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}
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pub fn vendor_and_device_id(&self) -> (u16, u16) {
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let id = self.read::<u32>(0);
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((id & 0xFFFF) as u16, (id >> 16) as u16)
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}
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pub fn device_id(&self) -> u16 {
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self.vendor_and_device_id().1
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}
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pub fn vendor_id(&self) -> u16 {
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self.vendor_and_device_id().0
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}
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pub fn interrupt_pin(&self) -> u8 {
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self.read(0x3D)
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}
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fn read<T>(&self, offset: u16) -> T {
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pci_read(self.bus, self.device, 0, offset)
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}
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fn write_u32(&self, offset: u16, value: u32) {
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pci_write(self.bus, self.device, 0, offset, value)
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}
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/// # Safety
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/// `self` must be a valid general PCI device.
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pub unsafe fn to_general_device(self) -> PciGeneralDevice {
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PciGeneralDevice(self)
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}
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}
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pub struct PciDeviceIterator {
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pub device: u8,
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}
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impl PciDeviceIterator {
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pub fn new() -> Self {
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let header_type: u32 = pci_read(0, 0, 0, 0);
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if header_type & 0x80 != 0 {
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unimplemented!("Multiple PCI host controllers are not supported")
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}
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Self { device: 0 }
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}
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}
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impl Iterator for PciDeviceIterator {
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type Item = PciDevice;
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fn next(&mut self) -> Option<Self::Item> {
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if self.device == 32 {
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return None;
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}
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let dev = self.device;
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self.device += 1;
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let vendor: u16 = pci_read(0, dev, 0, 0);
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if vendor == 0xFFFF {
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self.next()
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} else {
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Some(PciDevice::new(0, dev))
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}
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}
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}
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pub fn scan_pci_for_virtio_keyboard2() -> Option<VirtioPciCaps> {
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let device = PciDeviceIterator::new()
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.find(|device| device.vendor_and_device_id() == (0x1af4, 0x1052))
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.unwrap();
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let device = unsafe {
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// VirtIO keyboard is a general PCI device
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device.to_general_device()
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};
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None
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}
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pub fn scan_pci_for_virtio_keyboard() -> Option<VirtioPciCaps> {
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// Sur RISC-V Virt, on scanne généralement le bus 0
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for dev in 0..32 {
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let vdev: u32 = pci_read(0, dev, 0, 0x00);
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let vendor = (vdev & 0xffff) as u16;
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let device = (vdev >> 16) as u16;
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// On cherche le Vendor ID VirtIO (0x1AF4)
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// et le Device ID Keyboard (0x1012 ou 0x1052 pour Modern)
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if vendor == 0x1af4 && (device >= 0x1000 && device <= 0x107f) {
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// Dans ta boucle de scan, après avoir trouvé le device
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let interrupt_pin = (pci_read::<u32>(0, dev, 0, 0x3C) >> 8) & 0xFF; // Offset 0x3D
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let irq = 32 + (dev as u32 + interrupt_pin - 1) % 4;
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let old_val = pci_read::<u32>(0, 2, 0, 0x3C);
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// On garde les 24 bits du haut (Interrupt Pin, etc.) et on change les 8 bits du bas
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let new_val = (old_val & 0xFFFFFF00) | irq;
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pci_write(0, 2, 0, 0x3C, new_val);
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println!(
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"VirtIO Keyboard sur Slot {}, PIN {}, mappé sur IRQ PLIC {}",
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dev, interrupt_pin, irq
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); // ACTIVER l'accès mémoire et le bus mastering (PCI Command)
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let cmd = pci_read::<u32>(0, dev, 0, 0x04);
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pci_write(0, dev, 0, 0x04, cmd | 0x6);
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let mut common_cfg = 0;
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let mut notify_cfg = 0;
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let mut isr_cfg = 0;
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// On initialise le multiplicateur à 1 par défaut
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let mut notify_multiplier: u32 = 1;
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// 1. Activer le Bus Master et le Memory Space globalement pour ce périphérique avant de commencer
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let old_cmd = pci_read::<u32>(0, dev, 0, 0x04);
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pci_write(0, dev, 0, 0x04, old_cmd | 0x06);
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// 2. Boucle d'assignation des BARs (AVANT de lire les capabilities)
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let mut bar_idx = 0;
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while bar_idx < 6 {
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let bar_reg = 0x10 + (bar_idx * 4);
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let bar_val = pci_read::<u32>(0, dev, 0, bar_reg);
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// Si le BAR veut de la mémoire (bit 0 == 0) et n'est pas mappé
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if bar_val & 0x1 == 0 && (bar_val & 0xFFFF_FFF0) == 0 {
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let new_addr =
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0x5100_0000 + (dev as u32 * 0x100_000) + (bar_idx as u32 * 0x4000);
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println!("ALLOCATE BAR {} at {:x}", bar_idx, new_addr);
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pci_write(0, dev, 0, bar_reg, new_addr | (bar_val & 0xF));
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// Gérer les BAR 64-bits (ils consomment deux slots)
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if (bar_val >> 1) & 0x3 == 2 {
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println!("bar {} is 64 bits", bar_idx);
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pci_write(0, dev, 0, bar_reg + 4, 0);
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bar_idx += 1
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}
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pci_write(0, dev, 0, bar_reg, new_addr);
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let confirm = pci_read::<u32>(0, dev, 0, bar_reg);
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println!("BAR confirmé : {:x}", confirm);
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}
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bar_idx += 1
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}
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let mut cap_ptr = (pci_read::<u32>(0, dev, 0, 0x34) & 0xFF) as u16;
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while cap_ptr != 0 {
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let header: u32 = pci_read(0, dev, 0, cap_ptr);
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let cap_id = (header & 0xFF) as u8;
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let next_ptr = ((header >> 8) & 0xFF) as u16;
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let v_type = ((header >> 24) & 0xFF) as u8;
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if cap_id == 0x09 {
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// VirtIO Vendor Capability
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let bar_idx = (pci_read::<u32>(0, dev, 0, cap_ptr + 4) & 0xFF) as u8;
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let offset = pci_read::<u32>(0, dev, 0, cap_ptr + 8) as usize;
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// VirtIO : bar_idx doit être entre 0 et 5. 0xFF signifie "ignoré".
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if bar_idx <= 5 {
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let bar_reg_offset = 0x10 + (bar_idx as u16 * 4);
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let mut bar_val = pci_read::<u32>(0, dev, 0, bar_reg_offset);
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let bar_addr = (bar_val & 0xFFFF_FFF0) as usize;
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let final_addr = bar_addr + offset;
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match v_type {
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1 => {
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common_cfg = final_addr;
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println!("[VirtIO] CommonCfg trouvé à 0x{:x}", final_addr);
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}
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2 => {
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notify_cfg = final_addr;
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// TRÈS IMPORTANT : Lire le multiplicateur (offset 16 de la capability)
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notify_multiplier = pci_read(0, dev, 0, cap_ptr + 16);
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println!(
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"[VirtIO] NotifyCfg trouvé à 0x{:x} (mult: {})",
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final_addr, notify_multiplier
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);
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}
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3 => {
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isr_cfg = final_addr;
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println!("[VirtIO] IsrCfg trouvé à 0x{:x}", final_addr);
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}
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_ => {}
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}
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}
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}
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cap_ptr = next_ptr;
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}
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if common_cfg != 0 && notify_cfg != 0 && isr_cfg != 0 {
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return Some(VirtioPciCaps {
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common_cfg,
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notify_cfg,
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isr_cfg,
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notify_multiplier,
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});
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}
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}
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}
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None
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}
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