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riscv64-kernel/ilm.ld
2026-01-30 16:22:53 +01:00

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/*
* ld directives the for barmetal RISCV
*/
OUTPUT_ARCH(riscv)
ENTRY(entry)
MEMORY {
RAM (wxa) : ORIGIN = 0x80000000, LENGTH = 128M
}
SECTIONS {
/* The kernel starts at 0x80000000 */
. = 0x80000000;
.text : {
KEEP(*(.text.entry))
*(.text .text.*)
} > RAM
.rodata : {
*(.rodata .rodata.*)
} > RAM
.data : {
*(.data .data.*)
} > RAM
.bss : ALIGN(8) {
__bss_start = .;
*(.bss .bss.*)
__bss_end = .;
} > RAM
_heap_start = ALIGN(8);
_heap_end = ORIGIN(RAM) + LENGTH(RAM);
}