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Makes scheduler works at the end of the interruption

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This commit is contained in:
Julien THILLARD
2026-02-11 16:39:36 +01:00
parent 6fc08b5dbb
commit 8a5c17482c
5 changed files with 139 additions and 204 deletions
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215
src/interrupt.rs
View File

@@ -1,19 +1,20 @@
use log::info;
use crate::{
boot::sbi::{EextensionID, TimerFunctionID}, clear_csr, generate_trap_handler, process::ExecutionContext, read_csr, riscv::disable_interrupt, set_csr, time::{IRQ_M_TIMER, setup_next_timer_interrupt}, write_csr
boot::sbi::{EextensionID, TimerFunctionID},
clear_csr, generate_trap_handler,
process::ExecutionContext,
read_csr,
riscv::disable_interrupt,
scheduler::scheduler,
set_csr,
time::{setup_next_timer_interrupt, IRQ_M_TIMER},
write_csr,
};
use core::arch::naked_asm;
use crate::time::{setup_timer_interrupt, timer_interrupt};
#[unsafe(no_mangle)]
unsafe extern "C" fn machine_trap_handler(
_interrupt_state: *const ExecutionContext,
mcause: u64,
mie: u64,
mip: u64,
) {
unsafe extern "C" fn machine_trap_handler(mcause: u64, mie: u64, mip: u64) {
let mepc = read_csr!(mepc);
let mtval = read_csr!(mtval);
if mcause & (1 << 63) == 0 {
@@ -89,7 +90,7 @@ unsafe extern "C" fn supervisor_trap_handler(
scause: u64,
_sie: u64,
_sip: u64,
) {
) -> *const ExecutionContext {
#[allow(clippy::single_match)]
match scause & !(1 << 63) {
5 => {
@@ -101,10 +102,12 @@ unsafe extern "C" fn supervisor_trap_handler(
in("a7") EextensionID::Time as u64,
);
}
timer_interrupt(unsafe { *interrupt_state });
timer_interrupt();
return scheduler(unsafe { *interrupt_state });
}
_ => {}
}
interrupt_state
}
pub unsafe fn setup_machine_trap_handler() {
@@ -116,8 +119,57 @@ pub unsafe fn setup_supervisor_trap_handler() {
setup_timer_interrupt();
}
generate_trap_handler! {
_machine_mode_trap, machine_trap_handler, m
#[unsafe(naked)]
#[unsafe(no_mangle)]
unsafe extern "C" fn _machine_mode_trap() {
naked_asm!(
"
addi sp, sp, -128
# Store the current frame
sd ra, 120(sp)
sd a0, 0(sp)
sd a1, 8(sp)
sd a2, 16(sp)
sd a3, 24(sp)
sd a4, 32(sp)
sd a5, 40(sp)
sd a6, 48(sp)
sd a7, 56(sp)
sd t0, 64(sp)
sd t1, 72(sp)
sd t2, 80(sp)
sd t3, 88(sp)
sd t4, 96(sp)
sd t5, 104(sp)
sd t6, 112(sp)
csrr a0, mcause
csrr a1, mie
csrr a2, mip
jal machine_trap_handler
# Restore registers
ld ra, 120(sp)
ld a0, 0(sp)
ld a1, 8(sp)
ld a2, 16(sp)
ld a3, 24(sp)
ld a4, 32(sp)
ld a5, 40(sp)
ld a6, 48(sp)
ld a7, 56(sp)
ld t0, 64(sp)
ld t1, 72(sp)
ld t2, 80(sp)
ld t3, 88(sp)
ld t4, 96(sp)
ld t5, 104(sp)
ld t6, 112(sp)
addi sp, sp, 128
mret"
)
}
generate_trap_handler! {
_supervisor_mode_trap, supervisor_trap_handler, s
@@ -129,13 +181,14 @@ macro_rules! generate_trap_handler {
#[unsafe(naked)]
#[unsafe(no_mangle)]
unsafe extern "C" fn $name() {
naked_asm!(
concat!("
naked_asm!(concat!(
"
mv t0, sp
addi sp, sp, -264
# Store the current frame
sd ra, 0(sp)
sd sp, 8(sp)
sd t0, 8(sp) // sp
sd gp, 16(sp)
sd tp, 24(sp)
sd a0, 32(sp)
@@ -170,92 +223,64 @@ macro_rules! generate_trap_handler {
csrr t0, sstatus
sd t0, 256(sp)
// sd ra, 120(sp)
// sd a0, 0(sp)
// sd a1, 8(sp)
// sd a2, 16(sp)
// sd a3, 24(sp)
// sd a4, 32(sp)
// sd a5, 40(sp)
// sd a6, 48(sp)
// sd a7, 56(sp)
// sd t0, 64(sp)
// sd t1, 72(sp)
// sd t2, 80(sp)
// sd t3, 88(sp)
// sd t4, 96(sp)
// sd t5, 104(sp)
// sd t6, 112(sp)
mv a0, sp
csrr a1, ", stringify!($mode),"cause
csrr a2, ", stringify!($mode),"ie
csrr a3, ", stringify!($mode),"ip
jal ", stringify!($jump_to), "
csrr a1, ",
stringify!($mode),
"cause
csrr a2, ",
stringify!($mode),
"ie
csrr a3, ",
stringify!($mode),
"ip
jal ",
stringify!($jump_to),
"
# Restore registers
ld t0, 248(sp)
ld t0, 248(a0)
csrw sepc, t0
ld t0, 256(sp)
csrw sstatus, t0
ld ra, 0(sp)
ld gp, 16(sp)
ld tp, 24(sp)
ld a0, 32(sp)
ld a1, 40(sp)
ld a2, 48(sp)
ld a3, 56(sp)
ld a4, 64(sp)
ld a5, 72(sp)
ld a6, 80(sp)
ld a7, 88(sp)
ld t0, 96(sp)
ld t1, 104(sp)
ld t2, 112(sp)
ld t3, 120(sp)
ld t4, 128(sp)
ld t5, 136(sp)
ld t6, 144(sp)
ld s0, 152(sp)
ld s1, 160(sp)
ld s2, 168(sp)
ld s3, 176(sp)
ld s4, 184(sp)
ld s5, 192(sp)
ld s6, 200(sp)
ld s7, 208(sp)
ld s8, 216(sp)
ld s9, 224(sp)
ld s10, 232(sp)
ld s11, 240(sp)
// ld t0, 256(a0)
// csrw sstatus, t0
ld ra, 0(a0)
ld sp, 8(a0)
ld gp, 16(a0)
ld tp, 24(a0)
ld a1, 40(a0)
ld a2, 48(a0)
ld a3, 56(a0)
ld a4, 64(a0)
ld a5, 72(a0)
ld a6, 80(a0)
ld a7, 88(a0)
ld t0, 96(a0)
ld t1, 104(a0)
ld t2, 112(a0)
ld t3, 120(a0)
ld t4, 128(a0)
ld t5, 136(a0)
ld t6, 144(a0)
ld s0, 152(a0)
ld s1, 160(a0)
ld s2, 168(a0)
ld s3, 176(a0)
ld s4, 184(a0)
ld s5, 192(a0)
ld s6, 200(a0)
ld s7, 208(a0)
ld s8, 216(a0)
ld s9, 224(a0)
ld s10, 232(a0)
ld s11, 240(a0)
ld sp, 8(sp)
ld a0, 32(a0)
// ld a0, 0(sp)
// ld a1, 8(sp)
// ld a2, 16(sp)
// ld a3, 24(sp)
// ld a4, 32(sp)
// ld a5, 40(sp)
// ld a6, 48(sp)
// ld a7, 56(sp)
// addi sp, sp, 264
// ld t0, 64(sp)
// ld t1, 72(sp)
// ld t2, 80(sp)
// ld t3, 88(sp)
// ld t4, 96(sp)
// ld t5, 104(sp)
// ld t6, 112(sp)
// ld ra, 120(sp)
addi sp, sp, 264
", stringify!($mode),"ret")
)
",
stringify!($mode),
"ret"
))
}
};
}