surv/riscv64-kernel
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Too late but it kinda works

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This commit is contained in:
Julien THILLARD
2026-02-11 15:19:10 +01:00
parent 53043fd3cd
commit 6fc08b5dbb
9 changed files with 570 additions and 59 deletions
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183
src/interrupt.rs
View File

@@ -1,17 +1,19 @@
use log::info;
use crate::{
boot::sbi::{TimeFID, EID},
clear_csr, generate_trap_handler, read_csr,
riscv::disable_interrupt,
set_csr,
time::{setup_next_timer_interrupt, IRQ_M_TIMER},
write_csr,
boot::sbi::{EextensionID, TimerFunctionID}, clear_csr, generate_trap_handler, process::ExecutionContext, read_csr, riscv::disable_interrupt, set_csr, time::{IRQ_M_TIMER, setup_next_timer_interrupt}, write_csr
};
use core::arch::naked_asm;
use crate::time::{setup_timer_interrupt, timer_interrupt};
#[unsafe(no_mangle)]
unsafe extern "C" fn machine_trap_handler(mcause: u64, mie: u64, mip: u64) {
unsafe extern "C" fn machine_trap_handler(
_interrupt_state: *const ExecutionContext,
mcause: u64,
mie: u64,
mip: u64,
) {
let mepc = read_csr!(mepc);
let mtval = read_csr!(mtval);
if mcause & (1 << 63) == 0 {
@@ -40,8 +42,8 @@ unsafe extern "C" fn machine_trap_handler(mcause: u64, mie: u64, mip: u64) {
#[allow(clippy::single_match)]
match eid {
c if c == EID::Time as u64 => match fid {
c if c == TimeFID::SetTimer as u64 => {
c if c == EextensionID::Time as u64 => match fid {
c if c == TimerFunctionID::SetTimer as u64 => {
clear_csr!(mip, 1 << 5);
setup_next_timer_interrupt();
}
@@ -82,7 +84,12 @@ unsafe extern "C" fn machine_trap_handler(mcause: u64, mie: u64, mip: u64) {
}
#[unsafe(no_mangle)]
unsafe extern "C" fn supervisor_trap_handler(scause: u64, _sie: u64, _sip: u64) {
unsafe extern "C" fn supervisor_trap_handler(
interrupt_state: *const ExecutionContext,
scause: u64,
_sie: u64,
_sip: u64,
) {
#[allow(clippy::single_match)]
match scause & !(1 << 63) {
5 => {
@@ -90,11 +97,11 @@ unsafe extern "C" fn supervisor_trap_handler(scause: u64, _sie: u64, _sip: u64)
core::arch::asm!(
"ecall",
in("a0") 0,
in("a6") TimeFID::SetTimer as u64,
in("a7") EID::Time as u64,
in("a6") TimerFunctionID::SetTimer as u64,
in("a7") EextensionID::Time as u64,
);
}
timer_interrupt();
timer_interrupt(unsafe { *interrupt_state });
}
_ => {}
}
@@ -124,52 +131,128 @@ macro_rules! generate_trap_handler {
unsafe extern "C" fn $name() {
naked_asm!(
concat!("
addi sp, sp, -128
addi sp, sp, -264
sd ra, 120(sp)
# Store the current frame
sd ra, 0(sp)
sd sp, 8(sp)
sd gp, 16(sp)
sd tp, 24(sp)
sd a0, 32(sp)
sd a1, 40(sp)
sd a2, 48(sp)
sd a3, 56(sp)
sd a4, 64(sp)
sd a5, 72(sp)
sd a6, 80(sp)
sd a7, 88(sp)
sd t0, 96(sp)
sd t1, 104(sp)
sd t2, 112(sp)
sd t3, 120(sp)
sd t4, 128(sp)
sd t5, 136(sp)
sd t6, 144(sp)
sd s0, 152(sp)
sd s1, 160(sp)
sd s2, 168(sp)
sd s3, 176(sp)
sd s4, 184(sp)
sd s5, 192(sp)
sd s6, 200(sp)
sd s7, 208(sp)
sd s8, 216(sp)
sd s9, 224(sp)
sd s10, 232(sp)
sd s11, 240(sp)
csrr t0, sepc
sd t0, 248(sp)
csrr t0, sstatus
sd t0, 256(sp)
// sd ra, 120(sp)
sd a0, 0(sp)
sd a1, 8(sp)
sd a2, 16(sp)
sd a3, 24(sp)
sd a4, 32(sp)
sd a5, 40(sp)
sd a6, 48(sp)
sd a7, 56(sp)
// sd a0, 0(sp)
// sd a1, 8(sp)
// sd a2, 16(sp)
// sd a3, 24(sp)
// sd a4, 32(sp)
// sd a5, 40(sp)
// sd a6, 48(sp)
// sd a7, 56(sp)
sd t0, 64(sp)
sd t1, 72(sp)
sd t2, 80(sp)
sd t3, 88(sp)
sd t4, 96(sp)
sd t5, 104(sp)
sd t6, 112(sp)
// sd t0, 64(sp)
// sd t1, 72(sp)
// sd t2, 80(sp)
// sd t3, 88(sp)
// sd t4, 96(sp)
// sd t5, 104(sp)
// sd t6, 112(sp)
csrr a0, ", stringify!($mode),"cause
csrr a1, ", stringify!($mode),"ie
csrr a2, ", stringify!($mode),"ip
mv a0, sp
csrr a1, ", stringify!($mode),"cause
csrr a2, ", stringify!($mode),"ie
csrr a3, ", stringify!($mode),"ip
jal ", stringify!($jump_to), "
ld a0, 0(sp)
ld a1, 8(sp)
ld a2, 16(sp)
ld a3, 24(sp)
ld a4, 32(sp)
ld a5, 40(sp)
ld a6, 48(sp)
ld a7, 56(sp)
# Restore registers
ld t0, 248(sp)
csrw sepc, t0
ld t0, 256(sp)
csrw sstatus, t0
ld ra, 0(sp)
ld gp, 16(sp)
ld tp, 24(sp)
ld a0, 32(sp)
ld a1, 40(sp)
ld a2, 48(sp)
ld a3, 56(sp)
ld a4, 64(sp)
ld a5, 72(sp)
ld a6, 80(sp)
ld a7, 88(sp)
ld t0, 96(sp)
ld t1, 104(sp)
ld t2, 112(sp)
ld t3, 120(sp)
ld t4, 128(sp)
ld t5, 136(sp)
ld t6, 144(sp)
ld s0, 152(sp)
ld s1, 160(sp)
ld s2, 168(sp)
ld s3, 176(sp)
ld s4, 184(sp)
ld s5, 192(sp)
ld s6, 200(sp)
ld s7, 208(sp)
ld s8, 216(sp)
ld s9, 224(sp)
ld s10, 232(sp)
ld s11, 240(sp)
ld t0, 64(sp)
ld t1, 72(sp)
ld t2, 80(sp)
ld t3, 88(sp)
ld t4, 96(sp)
ld t5, 104(sp)
ld t6, 112(sp)
ld sp, 8(sp)
ld ra, 120(sp)
// ld a0, 0(sp)
// ld a1, 8(sp)
// ld a2, 16(sp)
// ld a3, 24(sp)
// ld a4, 32(sp)
// ld a5, 40(sp)
// ld a6, 48(sp)
// ld a7, 56(sp)
// ld t0, 64(sp)
// ld t1, 72(sp)
// ld t2, 80(sp)
// ld t3, 88(sp)
// ld t4, 96(sp)
// ld t5, 104(sp)
// ld t6, 112(sp)
// ld ra, 120(sp)
addi sp, sp, 128
addi sp, sp, 264
", stringify!($mode),"ret")
)