Refactor

src/riscv.rs

@@ -1,3 +1,7 @@
+//! RISC-V CSR helpers and interrupt utilities.
+//!
+//! Small helpers to read/modify control and status registers and manage
+//! interrupt enable/disable states.
 #![allow(unused)]
 
 use core::arch::naked_asm;
@@ -18,24 +22,34 @@ impl SStatus {
     pub const SPIE: usize = 1 << 5;
 }
 
+/// Return the current machine interrupt enable state.
 pub fn get_interrupt_state() -> bool {
     (read_csr!(mstatus) & MStatus::MIE as u64) != 0
 }
+/// Return whether supervisor interrupts are currently enabled.
 pub fn get_supervisor_interrupt_state() -> bool {
     (read_csr!(sstatus) & SStatus::SIE as u64) != 0
 }
+/// Enable machine-level interrupts.
 pub fn enable_interrupt() {
     set_csr!(mstatus, MStatus::MIE);
 }
+/// Enable supervisor-level interrupts.
 pub fn enable_supervisor_interrupt() {
     set_csr!(sstatus, SStatus::SIE);
 }
+
+/// Disable machine-level interrupts.
 pub fn disable_interrupt() {
     clear_csr!(mstatus, MStatus::MIE);
 }
+
+/// Disable supervisor-level interrupts.
 pub fn disable_supervisor_interrupt() {
     clear_csr!(sstatus, SStatus::SIE);
 }
+
+/// Restore machine interrupt state from `previous_state`.
 pub fn restore_interrupt(previous_state: bool) {
     if previous_state {
         enable_interrupt();
@@ -43,6 +57,8 @@ pub fn restore_interrupt(previous_state: bool) {
         disable_interrupt();
     }
 }
+
+/// Restore supervisor interrupt state from `previous_state`.
 pub fn restore_supervisor_interrupt(previous_state: bool) {
     if previous_state {
         enable_supervisor_interrupt();