41 lines
1.1 KiB
Scala
41 lines
1.1 KiB
Scala
package projet
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import chisel3._
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import chisel3.util._
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class VgaIp extends Module {
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val io = IO(new Bundle {
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val clk = Input(Clock())
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val bus = Flipped(new BusInterface)
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val hs = Output(Bool())
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val vs = Output(Bool())
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val r = Output(UInt(5.W))
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val g = Output(UInt(6.W))
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val b = Output(UInt(5.W))
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})
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withClock(io.clk) {
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val sync = Module(new GeneSync())
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io.hs := RegNext(sync.io.hsync)
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io.vs := RegNext(sync.io.vsync)
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val img_sync = RegNext(sync.io.img)
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val index = RegNext(sync.io.x(2, 1))
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io.bus.en := true.B
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io.bus.be := VecInit(false.B, false.B, false.B, false.B)
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io.bus.wdata := 0.U
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val addr = 80.U * sync.io.y(8, 1) + sync.io.x(9, 3)
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// Adresse mot dans la ram vidéo
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io.bus.addr := addr(14, 0) ## 0.U(2.W)
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val pixel = MuxCase(0.U,
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(0 until 4).map {i =>
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(index === i.U) -> io.bus.rdata(8 * (3 - i) + 7, 8 * (3 - i))
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})
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io.r := Mux(img_sync, pixel(7, 6)<<3, 0.U)
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io.g := Mux(img_sync, pixel(5, 3)<<3, 0.U)
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io.b := Mux(img_sync, pixel(2, 0)<<2, 0.U)
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}
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}
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