72 lines
2.4 KiB
Scala
72 lines
2.4 KiB
Scala
package projet
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import scala.io.Source
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import scala.collection.mutable.ListBuffer
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import org.scalatest.freespec.AnyFreeSpec
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import chisel3.simulator.scalatest.ChiselSim
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object ZzTopCommon extends AnyFreeSpec with ChiselSim {
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def expectedValuesFromAsm(path: String): Seq[BigInt] = {
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Source
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.fromFile(path)
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.getLines()
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.filter(_.trim().startsWith("# expected:"))
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.map(
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_.trim().stripPrefix("# expected:")
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.split(",")
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.map(_.trim)
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.filter(_.nonEmpty)
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.map(str => {
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if (str.charAt(0) == '-') {
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BigInt("FFFFFFFFFFFFFFFF", 16) -
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BigInt(str.substring(1), 16) + 1
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} else {
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BigInt(str, 16)
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}
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})
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.toSeq
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)
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.fold(Seq.empty)((acc, line) => {
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acc.concat(line)
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})
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}
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def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {
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val prefix = s"🛑 $msg\n"
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val traceStr =
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if (trace.nonEmpty)
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"Trace:\n" + trace.map(" - " + _).mkString("\n") + "\n"
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else ""
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fail(prefix + traceStr)
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}
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def expectNextValue(
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dut: ZzTop,
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expected: BigInt,
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timeout: Int,
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trace: ListBuffer[String]
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): Unit = {
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var cycles = 0
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val clock_per_cpucycle = 2;
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dut.clock.step(
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clock_per_cpucycle
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) // Attente d'un cycle proc (clock_per_cpucycle cycles systeme)
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// Attendre une écriture dans x31
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while (!dut.io.valid_x31.get.peek().litToBoolean && cycles < timeout) {
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dut.clock.step(clock_per_cpucycle) // Attente d'un cycle proc
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cycles += 1
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trace += f"Attente $cycles cycles"
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}
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if (cycles < timeout) {
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// Vérifier la nouvelle valeur
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val got = dut.io.x31.get.peek().litValue
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trace += f"Valeur attendue = 0x$expected%016X, reçue = 0x$got%016X"
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if (got != expected) failTrace("Mauvaise sortie", trace)
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} else {
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trace += f"Valeur attendue = 0x$expected%016X, reçue = ⏰"
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failTrace("Simulation bloquée", trace)
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}
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}
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}
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