72 lines
2.1 KiB
Scala
72 lines
2.1 KiB
Scala
package projet.op
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import chisel3._
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import chisel3.util.switch
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import projet.CUInterface
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import projet.AluOpCode
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import chisel3.util.is
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import projet.OpType
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object OpRW {
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// Implements functions for all instruction of the opImm, w kind
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def opRW(io: CUInterface) = {
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val funct3 = io.instruction(14, 12);
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val funct7 = io.instruction(31, 25);
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// Meaning of Funct3 in the context of an OpImm instruction
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object Funct3 extends ChiselEnum {
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// Type I
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val AdditionSubstraction = "b000".U
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val SLLW = "b001".U
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val ShiftRight = "b101".U
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// Unimplemented
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val ShiftWordRight = "b101".U // Right shifts
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}
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object AdditionSubstractionFunct7 extends ChiselEnum {
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val ADDW = "b0000000".U
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val SUBW = "b0100000".U
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}
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object ShiftWordRightFunct7 extends ChiselEnum {
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val SRLW = "b0000000".U
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val SRAW = "b0100000".U
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}
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io.reg_file_we := true.B // Write to regfile
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io.alu_word_mode := true.B
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io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
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io.mux_rega_pc := true.B;
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io.mux_alu_imm := true.B;
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switch(funct3) {
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// Type I
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is(Funct3.AdditionSubstraction) {
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switch(funct7) {
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is(AdditionSubstractionFunct7.ADDW) {
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io.alu_opcode := AluOpCode.Add
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}
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is(AdditionSubstractionFunct7.SUBW) {
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io.alu_opcode := AluOpCode.Sub
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}
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}
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}
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is(Funct3.SLLW) {
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io.alu_opcode := AluOpCode.ShiftLeft
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}
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is(Funct3.ShiftWordRight) {
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switch(funct7) {
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is(ShiftWordRightFunct7.SRAW) {
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io.alu_opcode := AluOpCode.ShiftArithmeticRight
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}
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is(ShiftWordRightFunct7.SRLW) {
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io.alu_opcode := AluOpCode.ShiftRight
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}
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}
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}
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}
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}
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}
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