79 lines
2.0 KiB
Scala
79 lines
2.0 KiB
Scala
package projet.op
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import chisel3._
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import chisel3.util.switch
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import projet.CUInterface
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import projet.AluOpCode
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import chisel3.util.is
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import projet.DMemSize
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import projet.OpType
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object OpLoad {
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// Implements functions for all instruction of the OpLoad kind
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def opLoad(io: CUInterface) = {
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val funct3 = io.instruction(14, 12);
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// Meaning of Funct3 in the context of an OpLoad instruction
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object Funct3 extends ChiselEnum {
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// Zero extend
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val LB = "b000".U
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val LH = "b001".U
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val LW = "b010".U
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// Sign extend
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val LBU = "b100".U
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val LHU = "b101".U
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val LWU = "b110".U
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// Arch width
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val LD = "b011".U
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}
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io.optype := OpType.I
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io.alu_opcode := AluOpCode.Add
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io.mux_alu_imm := true.B
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io.mux_rega_pc := true.B
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io.mux_regb_imm := false.B
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io.mux_writeback_pc := true.B;
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io.mux_executeout_dout := false.B;
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io.reg_file_we := true.B
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io.memory_en := true.B
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io.memory_we := false.B
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switch(funct3) {
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// Byte load
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is(Funct3.LB) {
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io.memory_size := DMemSize.Byte
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io.memory_sign_extend := true.B;
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}
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is(Funct3.LBU) {
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io.memory_size := DMemSize.Byte
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}
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// Half load
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is(Funct3.LH) {
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io.memory_size := DMemSize.Half
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io.memory_sign_extend := true.B;
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}
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is(Funct3.LHU) {
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io.memory_size := DMemSize.Half
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}
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// Word load
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is(Funct3.LW) {
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io.memory_size := DMemSize.Word
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}
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is(Funct3.LWU) {
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io.memory_size := DMemSize.Word
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io.memory_sign_extend := true.B;
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}
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// Long load
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is(Funct3.LD) {
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io.memory_size := DMemSize.Long
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io.memory_sign_extend := true.B;
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}
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}
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}
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}
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