77 lines
2.4 KiB
Scala
77 lines
2.4 KiB
Scala
package projet
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import chisel3._
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class ZzTop(file: String = "", sim: Boolean = true) extends Module {
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val io = IO(new Bundle {
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// Interface debug minimale
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val switch = Input(UInt(4.W))
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val led = Output(UInt(4.W))
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val push = Input(UInt(3.W))
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// Debug simu pour ne pas s'embeter avec le switch dans le testbench
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val x31 = if (sim) Some(Output(UInt(32.W))) else None
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val valid_x31 = if (sim) Some(Output(Bool())) else None
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// Port vga
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val hs = Output(Bool())
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val vs = Output(Bool())
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val r = Output(UInt(5.W))
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val g = Output(UInt(6.W))
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val b = Output(UInt(5.W))
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})
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val clkg = Module(new ClockGen(12, sim)) // ~ 10 MHz
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// clock et reset sont les signaux implicites
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clkg.io.clk_in1 := clock
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clkg.io.reset := reset
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val rst = (reset.asBool || !clkg.io.locked).asAsyncReset
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// Ces deux IPs doivent tourner à 125 MHz
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val vmem = Module(new IDMem(sim, 17))
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vmem.io.clki := clkg.io.clk_out2 // Clock du pixel
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vmem.io.clkd := clkg.io.clk_out1 // Clock du reste du système
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val vgad = Module(new VgaIp)
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vgad.io.clk := clkg.io.clk_out2 // Clock pixel
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// Expose core for testing usage
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val core = withClockAndReset(clkg.io.clk_out1, rst) {
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val interconnect = Module(new BusInterconnect)
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val core = Module(new Rv32i(sim))
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val dmem = Module(new IDMem(sim, 16, file))
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val ldip = Module(new LedIp)
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val clnt = Module(new CLint)
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dmem.io.clki := clkg.io.clk_out1 // Ou clock, non ?
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dmem.io.clkd := clkg.io.clk_out1 //
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ldip.io.switch := io.switch
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ldip.io.button := io.push
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ldip.io.x31 := core.io.x31
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io.led := ldip.io.led
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if (sim) {
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io.x31.get := core.io.x31
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io.valid_x31.get := core.io.valid_x31.get
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}
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interconnect.io.master <> core.io.dbus
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interconnect.io.dmem <> dmem.io.dbus
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interconnect.io.ldip <> ldip.io.bus
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interconnect.io.clnt <> clnt.io.bus
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interconnect.io.vmem <> vmem.io.dbus
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// connexion ad-hoc pour le bus d'instructions
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dmem.io.ibus <> core.io.ibus
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// connexion ad-hoc pour l'IP Vga
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vmem.io.ibus <> vgad.io.bus
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io.hs := vgad.io.hs
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io.vs := vgad.io.vs
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io.r := vgad.io.r
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io.g := vgad.io.g
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io.b := vgad.io.b
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core
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}
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}
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