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fmn_processor/bench/tests/op
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Albin Chaboissier cfce066cd7 Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
..
add.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
addi.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
addiw.s
Implements (mostly untested) rv64i)
2025-11-12 18:02:14 +01:00
addw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
and.s
Add tests for stage 7
2025-11-06 18:52:31 +01:00
andi.s
Refactor tests
2025-11-06 16:34:17 +01:00
auipc.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
beq.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
bge.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
bgeu.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
blt.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
bltu.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
bne.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
div.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
divu.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
divuw.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
divw.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
jal.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
jalr.s
Improves test for jumps
2025-11-14 08:55:07 +01:00
lb.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
lbu.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
ld.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
lh.s
Corrects critical mistake where core tried to bypass even if previous instruction did not write-back
2025-11-15 00:57:59 +01:00
lhu.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
li.s
Adds a test for load immediate (li) pseudo instruction
2025-11-11 11:05:05 +01:00
lui.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
lw.s
Corrects critical mistake where core tried to bypass even if previous instruction did not write-back
2025-11-15 00:57:59 +01:00
lwu.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
mul.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
mulh.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
mulhsu.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
mulhu.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
mulw.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
or.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
ori.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
rem.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
remu.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
remuw.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
remw.s
Reduces LUT needed by mul extension
2025-11-14 19:08:41 +01:00
sb.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
sd.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
sh.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
sll.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
slli.s
Moves control unit ops to separate files
2025-11-12 11:53:28 +01:00
slliw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
sllw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
slt.s
Stage 7: Register to register operations, all tests passing
2025-11-06 19:02:42 +01:00
slti.s
Implements stage 6: tests passing
2025-11-06 18:38:32 +01:00
sltiu.s
Implements stage 6: tests passing
2025-11-06 18:38:32 +01:00
sltu.s
Add tests for stage 7
2025-11-06 18:52:31 +01:00
sra.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
srai.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
sraiw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
sraw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
srl.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
srli.s
Moves control unit ops to separate files
2025-11-12 11:53:28 +01:00
srliw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
srlw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
sub.s
Lays groundword for Rv64i extension
2025-11-10 16:38:40 +01:00
subw.s
Rv64i : passing test
2025-11-13 09:49:18 +01:00
sw.s
Modifies test slightly because now RAM is relocated to 0x10000
2025-11-15 01:26:49 +01:00
xor.s
Add tests for stage 7
2025-11-06 18:52:31 +01:00
xori.s
Implements stage 6: tests passing
2025-11-06 18:38:32 +01:00