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036f432d76
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Stage 9: Full implemntation + passing tests
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2025-11-07 18:03:45 +01:00 |
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2117f8155e
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Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa
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2025-11-07 17:04:37 +01:00 |
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a897778605
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Modifies alu for branching instructions
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2025-11-07 17:04:05 +01:00 |
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6dd2cf0298
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Refactor Spec files
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2025-11-07 15:54:04 +01:00 |
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ea211d8a74
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Reduces CPU cycles to 2 clock cycles for faster testing/simulation
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2025-11-07 15:34:08 +01:00 |
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e83e7c11c1
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Stage 8: all tests passing
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2025-11-07 15:27:15 +01:00 |
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c88662403e
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Attempts to implement jalr, test not passing
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2025-11-07 13:37:46 +01:00 |
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3761077b84
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Merges build.sc
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2025-11-07 12:03:27 +01:00 |
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479526a0fb
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Adds parallel testing
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2025-11-07 12:02:17 +01:00 |
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99c5e0c78c
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Changes binary notation in ControlUnit to make formatter happy
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2025-11-07 11:53:09 +01:00 |
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9c5313522d
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Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa
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2025-11-07 11:51:43 +01:00 |
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cbf7ec9ad3
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Add jal instruction
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2025-11-07 11:51:33 +01:00 |
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0e991583b9
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Changes binary notation in ControlUnit to make formatter happy
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2025-11-07 10:41:09 +01:00 |
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c2c16d9672
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Stage 7: Register to register operations, all tests passing
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2025-11-06 19:02:42 +01:00 |
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1c829366de
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Implements stage 6: tests passing
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2025-11-06 18:38:32 +01:00 |
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2779471523
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Stage 6: implementation, untested
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2025-11-06 16:18:01 +01:00 |
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1462563e39
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Implements stage 5
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2025-11-05 20:01:41 +01:00 |
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5df85799ef
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Stage 4: Implements auipc
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2025-11-05 18:40:27 +01:00 |
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3870e05613
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Implements stage 3
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2025-11-05 17:23:33 +01:00 |
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41c5da1a64
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Formats code
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2025-11-04 18:08:45 +01:00 |
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fa60ce372f
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Implements stage 2
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2025-11-04 18:06:00 +01:00 |
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7956338fbc
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Stage 1 + removes hardcoded paths
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2025-11-04 15:41:33 +01:00 |
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Olivier Muller
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ff440776bb
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Squelette du projet
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2025-11-03 11:00:11 +01:00 |
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