Squelette du projet

src/main/scala/projet/Rv32i.scala

@@ -0,0 +1,14 @@
+package projet
+
+import chisel3._
+
+class Rv32i(sim: Boolean = true) extends Module {
+  val io = IO(new Bundle {
+    val ibus = Flipped(new BusInterface)
+    val dbus = Flipped(new BusInterface)
+    val x31 = Output(UInt(32.W))
+    val valid_x31  = if (sim)  Some(Output(Bool())) else None
+  })
+
+  locally(sim)
+}