Squelette du projet
This commit is contained in:
Olivier Muller
186
Makefile
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186
Makefile
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COMMON_DIR := common
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TOCLEAN = $(filter %log %.jou %.rpt %.mmi %.dcp %.csv\
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%.wdb vivado% updatemem% usage_statistics_webtalk%,$(wildcard *))
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TOCLEAN += $(wildcard _*) .Xil out RTL build download.bit
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# macro de verbosité
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VERB := 0
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q = $(if $(filter 1, $(VERB)),$1,\
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$(if $2,@echo $2 && $1 > $3 2>&1, @$1))
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# macro de vérification de variables d'environnement
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check_vars = $(foreach v, $1, $(if $(filter undefined, $(origin $v)),\
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if [ "$v" = "XILINX_VIVADO" ]; then \
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echo "⚠️ Tapez : source /bigsoft/Xilinx/Vivado/2019.1/settings64.sh"; \
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exit 1; \
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else \
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echo "⚠️ ⚡⚡ Variable d'environnement $v manquante ⚡⚡⚠️ "; \
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$(MAKE) --no-print-directory help; \
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exit 1; \
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fi;))
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all: help
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help:
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@awk 'BEGIN {FS = ":.*##!"; printf "Usage: make \033[32m<commande>\033[0m \
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[PROG=<nom du fichier de test sans extension>] \
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[CYCLES=durée de la simulation] [VERB=1 pour la verbosité]\
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\nCommandes par \033[36mcatégories :\n"} \
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/^[a-zA-Z0-9_-]+:.*##!/ { printf " \033[32m%-15s\033[0m %s\n", $$1, $$2 } \
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/^##@/ { printf "\n\033[36m%s\033[0m\n", substr($$0, 5) }' $(MAKEFILE_LIST)
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.PHONY: synthese fpga clean compile autotest simulation
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###############################################################################
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## Partie Compilation
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BENCH_DIR := bench
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MEM_DIR := $(BENCH_DIR)/mem
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SRC_SW := $(wildcard $(BENCH_DIR)/*.s)
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SRC_SW += $(wildcard $(BENCH_DIR)/*.c) # Contient tous les .s et .c du projet
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MEM = $(addprefix $(MEM_DIR)/, $(addsuffix .mem, $(basename $(notdir $(SRC_SW))))) # Tous les .mem du projet
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PREFIX := $(shell command -v riscv64-unknown-elf-gcc >/dev/null 2>&1 && echo riscv64-unknown-elf- || echo /matieres/3MMFMN/riscv32/bin/riscv32-unknown-elf-)
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CC := $(PREFIX)gcc
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OBJDUMP := $(PREFIX)objdump
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OBTOMEM := common/objtomem.awk
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## Flags
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ASFLAGS :=-march=rv32i -mabi=ilp32 -ffreestanding -nostdlib -T $(BENCH_DIR)/link.ld
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CFLAGS :=$(ASFLAGS)
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ELFFLAGS :=$(ASFLAGS) $(MEM_DIR)/crt.o -Os -fno-unroll-loops
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ODFLAGS :=-j .text -j .rodata -j .data -s
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.PRECIOUS: $(MEM_DIR)/%.elf
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compile: $(MEM)
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$(MEM_DIR):
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@mkdir -p $@
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$(MEM_DIR)/crt.o: $(BENCH_DIR)/crt.S |$(MEM_DIR)
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$(call q,\
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$(CC) $(CFLAGS) -c $< -o $@ , " Compilation crt",$@.log)
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$(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o|$(MEM_DIR)
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$(call q,\
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$(CC) $(ELFFLAGS) $< -o $@ , " Compilation $<",$@.log)
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$(MEM_DIR)/%.elf: $(BENCH_DIR)/%.s |$(MEM_DIR)
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$(call q,\
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$(CC) $(CFLAGS) -o $@ $<, " Compilation $<",$@.log)
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$(MEM_DIR)/%.mem: $(MEM_DIR)/%.elf |$(MEM_DIR)
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$(call q,\
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$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk," Génération de $@",$@)
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###############################################################################
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##@ Simulation
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TOP := ZzTop
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TOP_REP := projet
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PATH_SRC := src/main/scala/$(TOP_REP)
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TOP_TEST := $(addsuffix Spec, $(TOP))
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CYCLES=500
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# Pour filtrer les tests dans une simulation
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ifdef PROG
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FILTRE_TEST:= -- -z "$(PROG)"
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endif
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mill:
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@curl -L https://raw.githubusercontent.com/lefou/millw/0.4.11/millw > mill
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@chmod +x mill
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autotest: mill compile ##! Lance la simulation automatique pour tous les tests ou juste celui fourni dans PROG
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@PROOT=$(PWD) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) $(FILTRE_TEST)
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simulation: compile ##! Lance gtkwave sur le test fourni dans PROG
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@$(call check_vars,PROG)
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@PROOT=$(PWD) PROG=$(PROG) CYCLES=$(CYCLES) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) -- -DemitVcd=1 -z "gtkwave"
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@gtkwave -a common/config.gtkw ./build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd
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###############################################################################
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##@ Passage sur carte
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SRC := $(wildcard $(PATH_SRC)/*.scala)
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SRC += $(wildcard src/main/resources/vsrc/*.v)
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FPGA := xc7z010-clg400-1
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SRC_SV := RTL/$(TOP_REP).$(TOP)/$(TOP).sv
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XILINX_PREFIX := $(XILINX_VIVADO)/bin/
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MEM_FILE:= $(MEM_DIR)/$(PROG).mem
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MMI_FILE:=$(TOP).mmi
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MEM_ID=$(shell grep -oP 'InstPath="\K[^"]+' $(MMI_FILE))
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PARAM = $(MEM_FILE) false # Variable pour passer des parametres au générateur SV
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.PRECIOUS: golden.bit
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# Créer un hash unique de la variable
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PROG_HASH := $(shell echo "$(PROG)" | md5sum | cut -d' ' -f1)
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RTL: $(SRC_SV) ##! Génération du SystemVerilog
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$(SRC_SV): mill $(SRC)
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$(call q, ./mill TPchisel.runMain common.EmitModule $(TOP_REP).$(TOP) $(PARAM) \
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, " Génération du SystemVerilog",/dev/null)
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$(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt: $(COMMON_DIR)/synthese.vivado.tcl RTL
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@$(call check_vars,XILINX_VIVADO)
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$(call q, \
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$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP)\
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, " Synthese",$@.log)
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synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt ##! Réalise la synthèse grossière pour évaluer les performances
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@echo "Rapport d'utilisation disponible dans $(TOP)_utilization.rpt"
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@echo "Rapport de timing disponible dans $(TOP)_timing.rpt"
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@python3 $(COMMON_DIR)/parse_report.py $^
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golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL
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@$(call check_vars,XILINX_VIVADO PROG)
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$(call q, \
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$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP) $@ $(MEM_FILE) \
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, " Génération du bitstream",$@.log)
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.prog_$(PROG_HASH):
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@rm -f .prog_* # Supprimer les anciens marqueurs
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@touch $@
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download.bit: golden.bit $(MEM_FILE) $(MMI_FILE) .prog_$(PROG_HASH)
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@$(call check_vars,XILINX_VIVADO PROG)
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$(call q, $(XILINX_PREFIX)updatemem -debug -force --meminfo $(MMI_FILE) --data $(MEM_FILE) --proc $(MEM_ID) --bit $< --out $@\
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, " Mise à jour du fichier du bitstream", $@.mem.log)
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check_usb:
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@lsusb | grep -q FT2232C || \
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( echo "❌ Carte Digilent non détectée (FT2232C manquante)" && \
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echo " → Vérifiez le câble USB, la carte ou changez de port." && \
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exit 1 )
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check_djtgcfg:
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@command -v djtgcfg >/dev/null 2>&1 || \
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( echo "❌ Outil djtgcfg introuvable." && \
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echo " → Changez de machine ou rebootez !" && \
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exit 1 )
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check_driver: check_djtgcfg
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@djtgcfg enum | grep -q "Digilent Zybo" || \
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( echo "❌ Aucun périphérique détecté par djtgcfg." && \
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echo " → Essayez un autre port USB ou vérifiez le câble." && \
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exit 1 )
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check_hw: check_usb check_driver
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fpga: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw ##! Génére le fichier de configuration du FPGA et le programme
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@$(call check_vars,XILINX_VIVADO)
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$(call q, \
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$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $(COMMON_DIR)/programFPGA.vivado.tcl -nolog -nojournal \
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-tclargs $< \
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, " Programmation",prog.log )
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##@ Nettoyage
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clean: ##! Fais le nettoyage
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$(call q, rm -rf $(TOCLEAN),)
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