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Working cube

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This commit is contained in:
Albin Chaboissier
2025-12-02 16:22:15 +01:00
parent 80a78441ef
commit fc2a63d7f1
3 changed files with 285 additions and 117 deletions
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239
bench/programs_rust/rot-cube/src/main.rs
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@@ -3,21 +3,60 @@
use core::{ use core::{
arch::asm, arch::asm,
f32::consts::PI,
ops::{Add, Mul, Sub}, ops::{Add, Mul, Sub},
slice::Chunks,
}; };
use fpga_lib::{ use fpga_lib::{
interface::{Buttons, Leds}, interface::{Buttons, Leds},
panic_handler, panic_handler,
register::X31, register::X31,
vga::{BLACK, BLUE, Color, FONT_WIDTH, GREEN, HEIGHT, RED, VGA, WHITE, WIDTH}, vga::{self, BLACK, BLUE, Color, FONT_WIDTH, GREEN, HEIGHT, RED, VGA, WHITE, WIDTH},
}; };
panic_handler! {} panic_handler! {}
#[derive(Clone, Copy)]
pub struct Vec3(f32, f32, f32); pub struct Vec3(f32, f32, f32);
#[derive(Clone, Copy)]
pub struct Mat3x3([[f32; 3]; 3]); pub struct Mat3x3([[f32; 3]; 3]);
pub fn map_float(x: f32, xmin: f32, xmax: f32, ymin: f32, ymax: f32) -> f32
{
((x - xmin) / (xmax - xmin)) * (ymax - ymin) + ymin
}
impl Mat3x3
{
fn rot_x(amount: f32) -> Self
{
Mat3x3([
[libm::cosf(amount), -libm::sinf(amount), 0.],
[libm::sinf(amount), libm::cosf(amount), 0.],
[0., 0., 1.],
])
}
fn rot_y(amount: f32) -> Self
{
Mat3x3([
[1., 0., 0.],
[0., libm::cosf(amount), -libm::sinf(amount)],
[0., libm::sinf(amount), libm::cosf(amount)],
])
}
fn rot_z(amount: f32) -> Self
{
Mat3x3([
[libm::cosf(amount), 0., -libm::sinf(amount)],
[0., 1., 0.],
[libm::sinf(amount), 0., libm::cosf(amount)],
])
}
}
impl Mul<Mat3x3> for Mat3x3 impl Mul<Mat3x3> for Mat3x3
{ {
type Output = Mat3x3; type Output = Mat3x3;
@@ -26,19 +65,37 @@ impl Mul<Mat3x3> for Mat3x3
{ {
Mat3x3([ Mat3x3([
[ [
rhs.0[0][0] * self.0[0][0], self.0[0][0] * rhs.0[0][0]
rhs.0[0][1] * self.0[1][0], + self.0[0][1] * rhs.0[1][0]
rhs.0[0][2] * self.0[2][0], + self.0[0][2] * rhs.0[2][0],
self.0[0][0] * rhs.0[0][1]
+ self.0[0][1] * rhs.0[1][1]
+ self.0[0][2] * rhs.0[2][1],
self.0[0][0] * rhs.0[0][2]
+ self.0[0][1] * rhs.0[1][2]
+ self.0[0][2] * rhs.0[2][2],
], ],
[ [
rhs.0[1][0] * self.0[0][1], self.0[1][0] * rhs.0[0][0]
rhs.0[1][1] * self.0[1][1], + self.0[1][1] * rhs.0[1][0]
rhs.0[1][2] * self.0[2][1], + self.0[1][2] * rhs.0[2][0],
self.0[1][0] * rhs.0[0][1]
+ self.0[1][1] * rhs.0[1][1]
+ self.0[1][2] * rhs.0[2][1],
self.0[1][0] * rhs.0[0][2]
+ self.0[1][1] * rhs.0[1][2]
+ self.0[1][2] * rhs.0[2][2],
], ],
[ [
rhs.0[2][0] * self.0[0][2], self.0[2][0] * rhs.0[0][0]
rhs.0[2][1] * self.0[1][2], + self.0[2][1] * rhs.0[1][0]
rhs.0[2][2] * self.0[2][2], + self.0[2][2] * rhs.0[2][0],
self.0[2][0] * rhs.0[0][1]
+ self.0[2][1] * rhs.0[1][1]
+ self.0[2][2] * rhs.0[2][1],
self.0[2][0] * rhs.0[0][2]
+ self.0[2][1] * rhs.0[1][2]
+ self.0[2][2] * rhs.0[2][2],
], ],
]) ])
} }
@@ -58,6 +115,16 @@ impl Mul<Vec3> for Mat3x3
} }
} }
impl Mul<f32> for Vec3
{
type Output = Vec3;
fn mul(self, rhs: f32) -> Self::Output
{
Vec3(self.0 * rhs, self.1 * rhs, self.2 * rhs)
}
}
const CUBE: [Vec3; 8] = [ const CUBE: [Vec3; 8] = [
Vec3(1., 1., 1.), Vec3(1., 1., 1.),
Vec3(1., 1., -1.), Vec3(1., 1., -1.),
@@ -70,31 +137,155 @@ const CUBE: [Vec3; 8] = [
]; ];
#[rustfmt::skip] #[rustfmt::skip]
const LINES: [usize; 24] = [ const LINES: [(usize, usize); 12] = [
// Face 1 // Face 1
0, 1, (0, 1),
1, 2, (1, 2),
2, 3, (2, 3),
3, 0, (3, 0),
// Face 2 // Face 2
4, 5, (4, 5),
5, 6, (5, 6),
6, 7, (6, 7),
7, 4, (7, 4),
// Cross faces // Cross faces
0, 4, (0, 4),
1, 5, (1, 5),
2, 6, (2, 6),
3, 7 (3, 7)
]; ];
const PRISM: [Vec3; 5] = [
Vec3(-1., 1., 1.),
Vec3(-1., 1., -1.),
Vec3(-1., -1., -1.),
Vec3(-1., -1., 1.),
Vec3(1., 0., 0.),
];
const PRISM_LINES: [(usize, usize); 8] = [
(0, 1),
(1, 2),
(2, 3),
(3, 0),
(0, 4),
(1, 4),
(2, 4),
(3, 4),
];
fn draw_line(xa: u16, ya: u16, xb: u16, yb: u16, color: Color)
{
// calculate dx & dy
let dx = xb as i16 - xa as i16;
let dy = yb as i16 - ya as i16;
// calculate steps required for generating pixels
let steps = if dx.abs() > dy.abs()
{
dx.abs()
}
else
{
dy.abs()
};
// calculate increment in x & y for each steps
let x_inc: f32 = dx as f32 / steps as f32;
let y_inc: f32 = dy as f32 / steps as f32;
// Put pixel for each step
let mut x = xa as f32;
let mut y = ya as f32;
for _ in 0..steps
{
//putpixel(round(X), round(Y), RED); // put pixel at (X,Y)
unsafe {
VGA::write_pixel_unsafe(x as u16, y as u16, color);
}
x += x_inc; // increment in x at each step
y += y_inc; // increment in y at each step
// generation step by step
}
}
pub fn draw_shape(positions: &[Vec3], lines: &[(usize, usize)], color: Color)
{
for (la, lb) in lines
{
let a = positions[*la] * 0.5;
let b = positions[*lb] * 0.5;
let xa = map_float(a.0, -1., 1., 0., 320.);
let ya = map_float(a.1, -1., 1., 0., 240.);
let xb = map_float(b.0, -1., 1., 0., 320.);
let yb = map_float(b.1, -1., 1., 0., 240.);
draw_line(xa as u16, ya as u16, xb as u16, yb as u16, color);
}
}
const CPU_FREQ: usize = 80_000_000;
#[unsafe(no_mangle)] #[unsafe(no_mangle)]
pub extern "C" fn main() -> ! pub extern "C" fn main() -> !
{ {
// CLEAR
for i in 0..320
{
for j in 0..240
{
unsafe {
VGA::write_pixel_unsafe(i, j, BLACK);
}
}
}
//draw_cube(&CUBE, WHITE);
let mut rx = 0.;
let mut ry = 0.;
let mut rz = 0.;
let mut prev_cube = CUBE;
let mut prev_prism = PRISM;
loop loop
{ {
core::hint::spin_loop(); rx += 0.03;
ry += 0.02;
rz += 0.05;
let mut cube = CUBE;
let mut prism = PRISM;
let mc = Mat3x3::rot_x(rx) * Mat3x3::rot_y(ry) * Mat3x3::rot_z(rz);
let mp = Mat3x3::rot_x(-PI / 2.) * Mat3x3::rot_y(rx) * Mat3x3::rot_z(0.1);
for x in cube.iter_mut()
{
*x = mc * *x;
}
for x in prism.iter_mut()
{
*x = mp * *x;
*x = *x * 0.5;
}
draw_shape(&prev_prism, &PRISM_LINES, BLACK);
draw_shape(&prism, &PRISM_LINES, BLUE);
draw_shape(&prev_cube, &LINES, BLACK);
draw_shape(&cube, &LINES, WHITE);
for _ in 0..(CPU_FREQ / 60)
{
unsafe {
asm!("nop");
}
}
prev_cube = cube;
prev_prism = prism;
} }
} }

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bitstreams/cube.bit Normal file
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163
tight_setup_hold_pins.txt
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@@ -1,120 +1,97 @@
+====================+====================+============================================+ +====================+====================+============================================+
| Launch Setup Clock | Launch Hold Clock | Pin | | Launch Setup Clock | Launch Hold Clock | Pin |
+====================+====================+============================================+ +====================+====================+============================================+
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[33]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[26]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[43]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[50]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[44]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[27]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[1]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[45]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[19]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[21]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[22]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[58]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[41]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[6]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[42]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[11]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[11]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[13]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[3]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[39]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[55]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[54]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[50]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[30]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[9]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[28]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[37]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[34]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[62]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[14]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[59]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[25]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[10]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[32]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[51]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[61]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[61]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[60]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[57]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[47]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[53]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[52]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[52]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[43]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[49]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[44]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[42]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[45]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[45]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[26]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[44]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[38]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[41]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[40]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[37]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[36]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[33]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[33]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[32]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[29]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[28]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[27]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[27]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[19]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[25]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[24]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[21]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[20]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[18]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[19]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[7]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[17]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[16]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[13]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[11]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[9]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[8]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[5]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[4]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[4]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[1]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[55]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[51]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[51]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[47]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[47]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[43]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[40]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[39]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[34]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[30]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[125]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[122]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[22]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[22]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[20]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[18]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[107]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[124]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[102]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[101]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[10]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[116]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[116]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[117]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[16]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[6]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[13]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[94]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[119]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[114]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[8]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[106]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[109]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[99]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[104]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[112]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[120]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[93]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[97]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/cycles_remaining_reg[6]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/cycles_remaining_reg[6]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[98]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[114]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[91]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[124]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[113]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[64]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[117]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[103]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[122]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[100]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[75]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[80]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[112]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[96]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[115]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[107]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[120]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[73]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[104]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[121]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[121]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[118]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[118]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[1]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[71]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[95]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[87]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[88]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[85]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[100]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[92]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[86]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[84]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[84]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[64]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[101]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[88]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[98]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[95]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[94]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[99]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/is_stalled_reg/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[92]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[79]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[85]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[83]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[83]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[96]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[67]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[74]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[68]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[90]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[77]/D | | clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[77]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[86]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[82]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[81]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[72]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[66]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[69]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/in_computation_reg/D |
+--------------------+--------------------+--------------------------------------------+ +--------------------+--------------------+--------------------------------------------+