Merges upstream

Makefile

@@ -3,7 +3,7 @@ FPGA_BOARD = zybo_z7_10
 
 TOCLEAN = $(filter %log %.jou %.rpt %.mmi %.dcp %.csv\
                    %.wdb vivado% updatemem% usage_statistics_webtalk%,$(wildcard *))
-TOCLEAN += $(wildcard _*) .Xil out RTL build download.bit 
+TOCLEAN += $(wildcard _*) .Xil out RTL build download.bit $(MEM_DIR)
 
 # macro de verbosité
 VERB     := 0
@@ -101,7 +101,7 @@ autotest: mill test-bench/mem/tests/$(PROG).mem ##! Lance la simulation automati
 testall: mill compile
 	@PROOT=$(PWD) NPROC=$(shell nproc) ./mill TPchisel.test.testOnly $(TOP_REP).ZzTopAllSpec
 
-simulation: compile ##! Lance gtkwave sur le test fourni dans PROG
+simulation: mill compile ##! Lance gtkwave sur le test fourni dans PROG
 	@$(call check_vars,PROG)
 	@PROOT=$(PWD) PROG=$(PROG) CYCLES=$(CYCLES) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) -- -DemitVcd=1 -z "gtkwave"
 	@gtkwave -a common/config.gtkw ./build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd
@@ -163,5 +163,11 @@ flash: download.bit
 	openFPGALoader -b $(FPGA_BOARD) $<
 
 ##@ Nettoyage
+TMPREP = /scratch/$(LOGNAME)
 clean: ##! Fais le nettoyage
+<<<<<<< HEAD
 	rm -rf $(TOCLEAN) 
+=======
+	$(call q, rm -rf $(TOCLEAN),) 
+	@if [ -e $(TMPREP) ] && [ ! -d $(TMPREP) ]; then rm -f $(TMPREP) ;fi
+>>>>>>> d19b059cb74c870536545638e0a521dbf4b485a8