Reduces CPU cycles to 2 clock cycles for faster testing/simulation

src/main/scala/projet/ZzTop.scala

@@ -20,7 +20,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
         val b = Output(UInt(5.W))
     })
 
-    val clkg = Module(new ClockGen(12, sim)) // ~ 10 MHz
+    val clkg = Module(new ClockGen(2, sim)) // ~ 10 MHz
     // clock et reset sont les signaux implicites
     clkg.io.clk_in1 := clock
     clkg.io.reset := reset