rv64im: passing tests

src/test/scala/projet/ZzTopCommon.scala

@@ -15,7 +15,14 @@ object ZzTopCommon extends AnyFreeSpec with ChiselSim {
                     .split(",")
                     .map(_.trim)
                     .filter(_.nonEmpty)
-                    .map(str => BigInt(str, 16))
+                    .map(str => {
+                        if (str.charAt(0) == '-') {
+                            BigInt("FFFFFFFFFFFFFFFF", 16) -
+                                BigInt(str.substring(1), 16) + 1
+                        } else {
+                            BigInt(str, 16)
+                        }
+                    })
                     .toSeq
             case None =>
                 Seq.empty
@@ -52,10 +59,10 @@ object ZzTopCommon extends AnyFreeSpec with ChiselSim {
         if (cycles < timeout) {
             // Vérifier la nouvelle valeur
             val got = dut.io.x31.get.peek().litValue
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = 0x$got%08X"
+            trace += f"Valeur attendue = 0x$expected%016X, reçue = 0x$got%016X"
             if (got != expected) failTrace("Mauvaise sortie", trace)
         } else {
-            trace += f"Valeur attendue = 0x$expected%08X, reçue = ⏰"
+            trace += f"Valeur attendue = 0x$expected%016X, reçue = ⏰"
             failTrace("Simulation bloquée", trace)
         }
     }