rv64im: passing tests

src/main/scala/projet/ControlUnit.scala

@@ -163,7 +163,8 @@ class ControlUnit() extends Module {
         // OpMw instructions
         is(OpCode.OpMw) {
             io.reg_file_we := true.B // Write to regfile
-            opMw(funct3, io);
+            io.alu_word_mode := true.B
+            opM(funct3, io);
         }
 
         // J instructions
@@ -614,36 +615,4 @@ class ControlUnit() extends Module {
             }
         }
     }
-    
-    // ~~ Rv64M ~~
-
-    // Implements functions for instructions of the M extension with word size
-    def opMw(funct3: UInt, io: CUInterface) = {
-        // Meaning of Funct3 in the context of an OpMw instruction
-        object Funct3 extends ChiselEnum {
-            val MULW = "b000".U
-            val DIVW = "b100".U
-            val DIVUW = "b101".U
-            val REMW = "b110".U
-            val REMUW = "b111".U
-        }
-
-        switch(funct3) {
-            is(Funct3.MULW) {
-                io.alu_opcode := AluOpCode.Mulw
-            }
-            is(Funct3.DIVW) {
-                io.alu_opcode := AluOpCode.Divw
-            }
-            is(Funct3.DIVUW) {
-                io.alu_opcode := AluOpCode.Divuw
-            }
-            is(Funct3.REMW) {
-                io.alu_opcode := AluOpCode.Remw
-            }
-            is(Funct3.REMUW) {
-                io.alu_opcode := AluOpCode.Remuw
-            }
-        }
-    }
 }