rv64im: passing tests

This commit is contained in:
2025-11-12 11:50:09 +01:00
parent 7a1221b16e
commit cfacd6a9fc
16 changed files with 321 additions and 60 deletions

View File

@@ -3,12 +3,10 @@ package projet
import chisel3._
import chisel3.util.switch
import chisel3.util.is
import chisel3.util.Cat
import chisel3.util.Fill
object AluOpCode extends ChiselEnum {
val Add, Sub, Mul, Mulh, Mulhsu, Mulhu, Div, Divu, Rem, Remu, Mulw,
Divw, Divuw, Remw, Remuw, And, Or, Xor, ShiftLeft, ShiftRight,
val Add, Sub, Mul, Mulh, Mulhsu, Mulhu, Div, Divu, Rem, Remu, Mulw, Divw,
Divuw, Remw, Remuw, And, Or, Xor, ShiftLeft, ShiftRight,
ShiftArithmeticRight, LessThanSigned, LessThanUnsigned,
GreaterEqualSigned, GreaterEqualUnsigned, Equal =
Value
@@ -58,6 +56,58 @@ class Alu extends Module {
out := io.a - io.b;
}
is(Mul) {
out := (io.a.asSInt * io.b.asSInt).asUInt;
}
is(Mulh) {
out := ((io.a.asSInt * io.b.asSInt) >> 64.U).asUInt;
}
is(Mulhsu) {
out := ((io.a.asSInt * io.b).asSInt >> 64.U).asUInt;
}
is(Mulhu) {
out := (io.a * io.b) >> 64.U;
}
is(Div) {
when(io.b === 0.U) {
when(io.word_mode) {
out := (-1).S(32.W).asUInt
}.otherwise {
out := (-1).S(64.W).asUInt
}
}.otherwise {
out := (io.a.asSInt / io.b.asSInt).asUInt;
}
}
is(Divu) {
when(io.b === 0.U) {
out := "xFFFFFFFFFFFFFFFF".U
}.otherwise {
out := io.a / io.b;
}
}
is(Rem) {
when(io.b === 0.U) {
out := io.a
}.otherwise {
out := (io.a.asSInt % io.b.asSInt).asUInt;
}
}
is(Remu) {
when(io.b === 0.U) {
out := io.a
}.otherwise {
out := io.a % io.b;
}
}
is(And) {
out := io.a & io.b;
}