Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa

src/main/scala/projet/Alu.scala

@@ -5,7 +5,7 @@ import chisel3.util.switch
 import chisel3.util.is
 
 object AluOpCode extends ChiselEnum {
-    val Add, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
+    val Add, Sub, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
         LessThanSigned, LessThanUnsigned, GreaterEqualSigned,
         GreaterEqualUnsigned, Equal = Value
 }
@@ -28,6 +28,10 @@ class Alu extends Module {
             io.out := io.a + io.b;
         }
 
+        is(Sub) {
+            io.out := io.a - io.b;
+        }
+
         is(And) {
             io.out := io.a & io.b;
         }

src/main/scala/projet/ControlUnit.scala

@@ -282,7 +282,7 @@ class ControlUnit() extends Module {
         // Meaning of Funct3 in the context of an OpR instruction
         object Funct3 extends ChiselEnum {
             // Type I
-            val ADD = "b000".U
+            val ADD_SUB = "b000".U
             val AND = "b111".U
             val OR = "b110".U
             val XOR = "b100".U
@@ -300,13 +300,25 @@ class ControlUnit() extends Module {
             val SRA = "b0100000".U
         }
 
+        object ADDFunct7 extends ChiselEnum {
+            val ADD = "b0000000".U
+            val SUB = "b0100000".U
+        }
+
         io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_rega_pc := true.B;
         io.mux_alu_imm := true.B;
         switch(funct3) {
             // Type I
-            is(Funct3.ADD) {
-                io.alu_opcode := AluOpCode.Add
+            is(Funct3.ADD_SUB) {
+                switch(funct7) {
+                    is(ADDFunct7.ADD) {
+                        io.alu_opcode := AluOpCode.Add
+                    }
+                    is(ADDFunct7.SUB) {
+                        io.alu_opcode := AluOpCode.Sub
+                    }
+                }
             }
 
             is(Funct3.AND) {