Add jal instruction

This commit is contained in:
2025-11-07 11:51:33 +01:00
parent c2c16d9672
commit cbf7ec9ad3
6 changed files with 90 additions and 41 deletions

View File

@@ -24,7 +24,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
// clock et reset sont les signaux implicites
clkg.io.clk_in1 := clock
clkg.io.reset := reset
val rst = (reset.asBool || !clkg.io.locked).asAsyncReset
val rst = reset.asBool || !clkg.io.locked
// Ces deux IPs doivent tourner à 125 MHz
val vmem = Module(new IDMem(sim, 17))
@@ -34,7 +34,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
vgad.io.clk := clkg.io.clk_out2 // Clock pixel
// Expose core for testing usage
val core = withClockAndReset(clkg.io.clk_out1, rst) {
withClockAndReset(clkg.io.clk_out1, rst) {
val interconnect = Module(new BusInterconnect)
val core = Module(new Rv32i(sim))
val dmem = Module(new IDMem(sim, 16, file))
@@ -70,7 +70,5 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
io.r := vgad.io.r
io.g := vgad.io.g
io.b := vgad.io.b
core
}
}