Add jal instruction
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@@ -24,7 +24,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
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// clock et reset sont les signaux implicites
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clkg.io.clk_in1 := clock
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clkg.io.reset := reset
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val rst = (reset.asBool || !clkg.io.locked).asAsyncReset
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val rst = reset.asBool || !clkg.io.locked
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// Ces deux IPs doivent tourner à 125 MHz
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val vmem = Module(new IDMem(sim, 17))
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@@ -34,7 +34,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
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vgad.io.clk := clkg.io.clk_out2 // Clock pixel
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// Expose core for testing usage
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val core = withClockAndReset(clkg.io.clk_out1, rst) {
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withClockAndReset(clkg.io.clk_out1, rst) {
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val interconnect = Module(new BusInterconnect)
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val core = Module(new Rv32i(sim))
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val dmem = Module(new IDMem(sim, 16, file))
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@@ -70,7 +70,5 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
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io.r := vgad.io.r
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io.g := vgad.io.g
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io.b := vgad.io.b
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core
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}
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}
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