Add jal instruction

src/main/scala/projet/ControlUnit.scala

@@ -10,16 +10,21 @@ class CUInterface extends Bundle {
     val alu_opcode = Output(AluOpCode())
     val optype = Output(OpType())
 
+    // True if the decoded instruction is a jump
+    val is_jump = Output(Bool())
+
     // Muxers
     // The naming convention is as follows : mux_xxx_yyy.
     // If the signal is hot, xxx is selected otherwise yyy is selected
     val mux_alu_imm = Output(Bool())
     val mux_rega_pc = Output(Bool())
     val mux_regb_imm = Output(Bool())
+    val mux_incrpc4_imm = Output(Bool())
+    val mux_regpc_executepc = Output(Bool())
 }
 
 object OpType extends ChiselEnum {
-    val U, I, IR = Value
+    val U, I, IR, J = Value
 }
 
 object OpCode extends ChiselEnum {
@@ -46,6 +51,8 @@ object OpCode extends ChiselEnum {
     // add, and, or, xor, sll, srl, sra, slt, stlu
     val OpR = 0b0110011.U;
 
+    // Type J
+    val JAL = 0b1101111.U
 }
 
 
@@ -55,9 +62,12 @@ class ControlUnit() extends Module {
     io.reg_file_we := false.B
     io.alu_opcode := AluOpCode.Add
     io.optype := OpType.U
+    io.is_jump := false.B;
     io.mux_alu_imm := true.B;
     io.mux_rega_pc := true.B;
     io.mux_regb_imm := true.B;
+    io.mux_incrpc4_imm := true.B;
+    io.mux_regpc_executepc := true.B;
 
     // Decode instruction
     val opcode = io.instruction(6, 0);
@@ -76,21 +86,33 @@ class ControlUnit() extends Module {
             io.alu_opcode := AluOpCode.Add 
             io.reg_file_we := true.B // Write to regfile
             io.mux_rega_pc := false.B // Send PC to ALU A
-            io.mux_alu_imm := false.B; // Send immu to ALU B
+            io.mux_regb_imm := false.B; // Send immu to ALU B
             io.optype := OpType.U
         }
 
         // OpImm instructions
         is(OpCode.OpImm) {
-            io.reg_file_we := true.B
+            io.reg_file_we := true.B // Write to regfile
             opImm(funct3, funct7, io);
         }
         
         // OpR instructions
         is(OpCode.OpR) {
-            io.reg_file_we := true.B
+            io.reg_file_we := true.B // Write to regfile
             opR(funct3, funct7, io);
         }
+
+        // J instructions
+        is(OpCode.JAL) {
+            io.alu_opcode := AluOpCode.Add 
+            io.reg_file_we := true.B // Write to regfile
+            io.mux_rega_pc := false.B // Send PC to ALU A
+            io.mux_regb_imm := false.B; // Send imm to ALU B
+            io.is_jump := true.B
+            io.mux_incrpc4_imm := false.B; // Send the immediate in PC
+            io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
+            io.optype := OpType.J
+        }
     }