Fixs JALR instruction

src/main/scala/projet/Rv64i.scala

@@ -119,6 +119,8 @@ class Rv64i(sim: Boolean = true) extends Module {
     // Select what to send on writeback line
     val execute_out = Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
     reg_execute_out := execute_out;
+    // Jalr line is directly the execute output
+    val jalr_line = execute_out
 
     reg_mux_executeout_dout := control_unit.io.mux_executeout_dout;
 
@@ -131,9 +133,9 @@ class Rv64i(sim: Boolean = true) extends Module {
 
     // Writeback pipelining registers
     reg_pc := Mux(
-        Delay.Delay(control_unit.io.mux_pcadder_writeback, 1, true.B),
+        control_unit.io.mux_pcadder_jalrwriteback,
         pc_adder_out,
-        writeback_line
+        jalr_line
     );
 
     dmem.io.data_in := rs2_data