diff --git a/bench/tests/op/jalr.s b/bench/tests/op/jalr.s new file mode 100644 index 0000000..1ad6ad1 --- /dev/null +++ b/bench/tests/op/jalr.s @@ -0,0 +1,15 @@ +# expected: 000000BA, 0000018, 0000000A + .text +_start: + jal x1, step1 + add x31, x0, 0x00A + jal x0, finish +step1: + jal x2, step2 + add x31, x0, 0x0AB # This instruction should never be executed + add x31, x0, 0x0BA + jalr x31, 0(x1) # Check if return address is written to x31 +step2: + jalr x0, 1(x2) # return to step1, but 1 further +finish: + nop diff --git a/src/main/scala/projet/ControlUnit.scala b/src/main/scala/projet/ControlUnit.scala index 0fea413..e4dc995 100644 --- a/src/main/scala/projet/ControlUnit.scala +++ b/src/main/scala/projet/ControlUnit.scala @@ -16,11 +16,27 @@ class CUInterface extends Bundle { // Muxers // The naming convention is as follows : mux_xxx_yyy. // If the signal is hot, xxx is selected otherwise yyy is selected + + // Sends alu or immediate to write back val mux_alu_imm = Output(Bool()) + + // Selects regA or pc for alu a val mux_rega_pc = Output(Bool()) + + // Selects regB or immediate for alu b val mux_regb_imm = Output(Bool()) + + // Selects 4 or immediate for pc incrementation val mux_incrpc4_imm = Output(Bool()) + + // Selects pc or previous pc for pc incrementation val mux_regpc_executepc = Output(Bool()) + + // Selects pc adder or write back for pc write + val mux_pcadder_writeback = Output(Bool()) + + // Selects pc or write back for register write + val mux_writeback_pc = Output(Bool()) } object OpType extends ChiselEnum { @@ -53,6 +69,9 @@ object OpCode extends ChiselEnum { // Type J val JAL = "b1101111".U + + // Type I + val JALR = "b1100111".U } class ControlUnit() extends Module { @@ -67,6 +86,8 @@ class ControlUnit() extends Module { io.mux_regb_imm := true.B; io.mux_incrpc4_imm := true.B; io.mux_regpc_executepc := true.B; + io.mux_writeback_pc := true.B; + io.mux_pcadder_writeback := true.B; // Decode instruction val opcode = io.instruction(6, 0); @@ -103,15 +124,31 @@ class ControlUnit() extends Module { // J instructions is(OpCode.JAL) { - io.alu_opcode := AluOpCode.Add + io.alu_opcode := AluOpCode.Add io.reg_file_we := true.B // Write to regfile io.mux_rega_pc := false.B // Send PC to ALU A io.mux_regb_imm := false.B; // Send imm to ALU B io.is_jump := true.B io.mux_incrpc4_imm := false.B; // Send the immediate in PC io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC + io.mux_pcadder_writeback := true.B; io.optype := OpType.J } + + is(OpCode.JALR) { + io.alu_opcode := AluOpCode.Add + + io.reg_file_we := true.B // Write to regfile + io.mux_writeback_pc := false.B // Write next instruction PC to rd + io.is_jump := true.B // Insert no-op to discard fetched next instruction + + io.mux_rega_pc := true.B // Send rs1 to ALU A + io.mux_regb_imm := false.B; // Send imm to ALU B + + io.mux_alu_imm := false.B; // Send alu out to write back line + io.mux_pcadder_writeback := false.B; // Set pc to writeback dest + io.optype := OpType.I + } } // Implements functions for all instruction of the opImm kind @@ -142,61 +179,50 @@ class ControlUnit() extends Module { io.mux_rega_pc := true.B; switch(funct3) { // Type I - is(Funct3.ADDI) - { + is(Funct3.ADDI) { io.alu_opcode := AluOpCode.Add io.optype := OpType.I } - is(Funct3.ANDI) - { + is(Funct3.ANDI) { io.alu_opcode := AluOpCode.And io.optype := OpType.I } - is(Funct3.ORI) - { + is(Funct3.ORI) { io.alu_opcode := AluOpCode.Or io.optype := OpType.I } - is(Funct3.XORI) - { + is(Funct3.XORI) { io.alu_opcode := AluOpCode.Xor io.optype := OpType.I } - is(Funct3.SLLI) - { + is(Funct3.SLLI) { io.alu_opcode := AluOpCode.ShiftLeft io.optype := OpType.I } - is(Funct3.SLTI) - { + is(Funct3.SLTI) { io.alu_opcode := AluOpCode.LessThanSigned io.optype := OpType.I } - is(Funct3.SLTIU) - { + is(Funct3.SLTIU) { io.alu_opcode := AluOpCode.LessThanUnsigned io.optype := OpType.I } // Type IR - is(Funct3.SRLI_SRAI) - { + is(Funct3.SRLI_SRAI) { io.optype := OpType.IR - switch(funct7) - { - is(IRFunct7.SRLI) - { + switch(funct7) { + is(IRFunct7.SRLI) { io.alu_opcode := AluOpCode.ShiftRight } - is(IRFunct7.SRAI) - { + is(IRFunct7.SRAI) { io.alu_opcode := AluOpCode.ShiftArithmeticRight } } @@ -232,53 +258,42 @@ class ControlUnit() extends Module { io.mux_alu_imm := true.B; switch(funct3) { // Type I - is(Funct3.ADD) - { + is(Funct3.ADD) { io.alu_opcode := AluOpCode.Add } - is(Funct3.AND) - { + is(Funct3.AND) { io.alu_opcode := AluOpCode.And } - is(Funct3.OR) - { + is(Funct3.OR) { io.alu_opcode := AluOpCode.Or } - is(Funct3.XOR) - { + is(Funct3.XOR) { io.alu_opcode := AluOpCode.Xor } - is(Funct3.SLL) - { + is(Funct3.SLL) { io.alu_opcode := AluOpCode.ShiftLeft } - is(Funct3.SLT) - { + is(Funct3.SLT) { io.alu_opcode := AluOpCode.LessThanSigned } - is(Funct3.SLTU) - { + is(Funct3.SLTU) { io.alu_opcode := AluOpCode.LessThanUnsigned } // Type IR - is(Funct3.SRL_SRA) - { - switch(funct7) - { - is(IRFunct7.SRL) - { + is(Funct3.SRL_SRA) { + switch(funct7) { + is(IRFunct7.SRL) { io.alu_opcode := AluOpCode.ShiftRight } - is(IRFunct7.SRA) - { + is(IRFunct7.SRA) { io.alu_opcode := AluOpCode.ShiftArithmeticRight } } diff --git a/src/main/scala/projet/Rv32i.scala b/src/main/scala/projet/Rv32i.scala index 7c0be1f..cd1083b 100644 --- a/src/main/scala/projet/Rv32i.scala +++ b/src/main/scala/projet/Rv32i.scala @@ -27,6 +27,8 @@ class Rv32i(sim: Boolean = true) extends Module { val execute_pc = Delay.Delay(reg_pc, 1, 0.U); // True if the instruction in the execute stage is a jump val is_jump = Delay.Delay(control_unit.io.is_jump, 1, false.B); + + // Insert no-op if jump val instruction = Mux(is_jump, 0b00000000000000000000000000010011.U, io.ibus.rdata); immediate_decoder.io.instruction := instruction @@ -35,7 +37,7 @@ class Rv32i(sim: Boolean = true) extends Module { reg_file.io.we := control_unit.io.reg_file_we // Increment PC each clock - reg_pc := Mux( + val pc_adder_out = Mux( control_unit.io.mux_regpc_executepc, reg_pc, execute_pc @@ -45,6 +47,7 @@ class Rv32i(sim: Boolean = true) extends Module { immediate_decoder.io.immediate ); + // Fetch instruction io.ibus.en := true.B; io.ibus.addr := reg_pc; @@ -72,7 +75,18 @@ class Rv32i(sim: Boolean = true) extends Module { ); alu.io.b := Mux(control_unit.io.mux_regb_imm, reg_file.io.rs2_data, imm); - reg_file.io.rd_data := Mux(control_unit.io.mux_alu_imm, alu.io.out, imm); + val writeback_line = Mux(control_unit.io.mux_alu_imm, alu.io.out, imm); + reg_file.io.rd_data := + Mux( + control_unit.io.mux_writeback_pc, + writeback_line, + reg_pc + ); + + reg_pc := Mux(control_unit.io.mux_pcadder_writeback, + pc_adder_out, + writeback_line + ); io.dbus.addr := 0.U; io.dbus.wdata := 0.U;