Lays groundword for Rv64i extension

Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory

src/main/scala/projet/ZzTop.scala

@@ -9,7 +9,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
         val led = Output(UInt(4.W))
         val push = Input(UInt(3.W))
         // Debug simu pour ne pas s'embeter avec le switch dans le testbench
-        val x31 = if (sim) Some(Output(UInt(32.W))) else None
+        val x31 = if (sim) Some(Output(UInt(64.W))) else None
         val valid_x31 = if (sim) Some(Output(Bool())) else None
 
         // Port vga
@@ -36,7 +36,7 @@ class ZzTop(file: String = "", sim: Boolean = true) extends Module {
     // Expose core for testing usage
     withClockAndReset(clkg.io.clk_out1, rst) {
         val interconnect = Module(new BusInterconnect)
-        val core = Module(new Rv32i(sim))
+        val core = Module(new Rv64i(sim))
         val dmem = Module(new IDMem(sim, 16, file))
         val ldip = Module(new LedIp)
         val clnt = Module(new CLint)