Lays groundword for Rv64i extension

Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory

src/main/scala/projet/RegFile.scala

@@ -7,16 +7,16 @@ class RegFile(sim: Boolean = false) extends Module {
         val rs1_addr = Input(UInt(5.W))
         val rs2_addr = Input(UInt(5.W))
         val rd_addr = Input(UInt(5.W))
-        val rd_data = Input(UInt(32.W))
+        val rd_data = Input(UInt(64.W))
         val we = Input(Bool())
-        val rs1_data = Output(UInt(32.W))
-        val rs2_data = Output(UInt(32.W))
+        val rs1_data = Output(UInt(64.W))
+        val rs2_data = Output(UInt(64.W))
 
-        val x31 = Output(UInt(32.W))
+        val x31 = Output(UInt(64.W))
         val valid_x31 = if (sim) Some(Output(Bool())) else None
     })
 
-    val regs = Mem(32, UInt(32.W))
+    val regs = Mem(32, UInt(64.W))
 
     if (sim) {
         when(reset.asBool) {