Lays groundword for Rv64i extension

Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory

src/main/scala/projet/LedIp.scala

@@ -7,14 +7,14 @@ import chisel3.util._
 \*/
 class LedIp extends Module {
     val io = IO(new Bundle {
-        val x31 = Input(UInt(32.W))
+        val x31 = Input(UInt(64.W))
         val switch = Input(UInt(4.W))
         val led = Output(UInt(4.W))
         val button = Input(UInt(3.W))
         val bus = new BusInterface
     })
 
-    io.bus.rdata := 0x01ed01ed.U // On lira ça si on lit !
+    io.bus.rdata := 0x01ed01ed01ed01edL.U // On lira ça si on lit !
 
     val dinReg = RegInit(0.U(32.W))
     val x31Reg = RegNext(io.x31) // On lit x31 en continue