Lays groundword for Rv64i extension

Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory

src/main/scala/projet/Alu.scala

@@ -5,18 +5,18 @@ import chisel3.util.switch
 import chisel3.util.is
 
 object AluOpCode extends ChiselEnum {
-    val Add, Sub, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
-        LessThanSigned, LessThanUnsigned, GreaterEqualSigned,
-        GreaterEqualUnsigned, Equal = Value
+    val Add, AddW, Sub, And, Or, Xor, ShiftLeft, ShiftRight,
+        ShiftArithmeticRight, LessThanSigned, LessThanUnsigned,
+        GreaterEqualSigned, GreaterEqualUnsigned, Equal = Value
 }
 
 class Alu extends Module {
     import AluOpCode._
 
     val io = IO(new Bundle {
-        val a = Input(UInt(32.W))
-        val b = Input(UInt(32.W))
-        val out = Output(UInt(32.W))
+        val a = Input(UInt(64.W))
+        val b = Input(UInt(64.W))
+        val out = Output(UInt(64.W))
         val opcode = Input(AluOpCode())
         val comp_result = Output(Bool())
     })
@@ -45,16 +45,16 @@ class Alu extends Module {
         }
 
         is(ShiftLeft) {
-            io.out := io.a << io.b(4, 0);
+            io.out := io.a << io.b(5, 0);
         }
 
         is(ShiftRight) {
-            io.out := io.a >> io.b(4, 0);
+            io.out := io.a >> io.b(5, 0);
         }
 
         is(ShiftArithmeticRight) {
             // >> means arithmetic shift for SInts
-            io.out := (io.a.asSInt >> io.b(4, 0)).asUInt;
+            io.out := (io.a.asSInt >> io.b(5, 0)).asUInt;
         }
 
         is(LessThanUnsigned) {