surv/fmn_processor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa

Browse Source
This commit is contained in:
Julien THILLARD
2025-11-07 11:51:43 +01:00
parent cbf7ec9ad3 0e991583b9
commit 9c5313522d
2 changed files with 167 additions and 177 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
.gitignore vendored
View File

@@ -6,3 +6,7 @@ mill*
bench/mem bench/mem
.metals .metals
.bloop .bloop
.rpt
.Xil
clockInfo.txt
.csv

78
src/main/scala/projet/ControlUnit.scala
View File

@@ -29,8 +29,8 @@ object OpType extends ChiselEnum {
object OpCode extends ChiselEnum { object OpCode extends ChiselEnum {
// Type U // Type U
val LUI = 0b0110111.U val LUI = "b0110111".U
val AUIPC = 0b0010111.U val AUIPC = "b0010111".U
// Type I + Type IR // Type I + Type IR
@@ -41,7 +41,7 @@ object OpCode extends ChiselEnum {
// addi, andi, ori, xori, slli, srli, srai, // addi, andi, ori, xori, slli, srli, srai,
// slti, sltiu // slti, sltiu
val OpImm = 0b0010011.U val OpImm = "b0010011".U
// Instruction format // Instruction format
// xxx rd, rs1, rs2 // xxx rd, rs1, rs2
@@ -49,13 +49,12 @@ object OpCode extends ChiselEnum {
// and writes back to a register // and writes back to a register
// add, and, or, xor, sll, srl, sra, slt, stlu // add, and, or, xor, sll, srl, sra, slt, stlu
val OpR = 0b0110011.U; val OpR = "b0110011".U;
// Type J // Type J
val JAL = 0b1101111.U val JAL = 0b1101111.U
} }
class ControlUnit() extends Module { class ControlUnit() extends Module {
val io = IO(new CUInterface()) val io = IO(new CUInterface())
@@ -115,39 +114,33 @@ class ControlUnit() extends Module {
} }
} }
// Implements functions for all instruction of the opImm kind // Implements functions for all instruction of the opImm kind
def opImm(funct3: UInt, funct7: UInt, io: CUInterface) = def opImm(funct3: UInt, funct7: UInt, io: CUInterface) = {
{
// Meaning of Funct3 in the context of an OpImm instruction // Meaning of Funct3 in the context of an OpImm instruction
object Funct3 extends ChiselEnum object Funct3 extends ChiselEnum {
{
// Type I // Type I
val ADDI = 0b000.U val ADDI = "b000".U
val SLTI = 0b010.U val SLTI = "b010".U
val SLTIU = 0b011.U val SLTIU = "b011".U
val XORI = 0b100.U val XORI = "b100".U
val ORI = 0b110.U val ORI = "b110".U
val ANDI = 0b111.U val ANDI = "b111".U
// Type IR // Type IR
val SLLI = 0b001.U val SLLI = "b001".U
val SRLI_SRAI = 0b101.U // Right shifts val SRLI_SRAI = "b101".U // Right shifts
} }
// Meaning of Funct7 in the context of SHIFTR IR instructions // Meaning of Funct7 in the context of SHIFTR IR instructions
object IRFunct7 extends ChiselEnum object IRFunct7 extends ChiselEnum {
{ val SRLI = "b0000000".U
val SRLI = 0b0000000.U val SRAI = "b0100000".U
val SRAI = 0b0100000.U
} }
io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
io.mux_alu_imm := true.B; io.mux_alu_imm := true.B;
io.mux_rega_pc := true.B; io.mux_rega_pc := true.B;
switch(funct3) switch(funct3) {
{
// Type I // Type I
is(Funct3.ADDI) is(Funct3.ADDI)
{ {
@@ -211,38 +204,33 @@ class ControlUnit() extends Module {
} }
} }
// Implements functions for all instruction of the opR kind // Implements functions for all instruction of the opR kind
def opR(funct3: UInt, funct7: UInt, io: CUInterface) = def opR(funct3: UInt, funct7: UInt, io: CUInterface) = {
{
// Meaning of Funct3 in the context of an OpR instruction // Meaning of Funct3 in the context of an OpR instruction
object Funct3 extends ChiselEnum object Funct3 extends ChiselEnum {
{
// Type I // Type I
val ADD = 0b000.U val ADD = "b000".U
val AND = 0b111.U val AND = "b111".U
val OR = 0b110.U val OR = "b110".U
val XOR = 0b100.U val XOR = "b100".U
val SLL = 0b001.U val SLL = "b001".U
val SLT = 0b010.U val SLT = "b010".U
val SLTU = 0b011.U val SLTU = "b011".U
// Arithmetic op (discriminate by Funct7) // Arithmetic op (discriminate by Funct7)
val SRL_SRA = 0b101.U val SRL_SRA = "b101".U
} }
// Meaning of Funct7 in the context of SHIFTR IR instructions // Meaning of Funct7 in the context of SHIFTR IR instructions
object IRFunct7 extends ChiselEnum object IRFunct7 extends ChiselEnum {
{ val SRL = "b0000000".U
val SRL = 0b0000000.U val SRA = "b0100000".U
val SRA = 0b0100000.U
} }
io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
io.mux_rega_pc := true.B; io.mux_rega_pc := true.B;
io.mux_alu_imm := true.B; io.mux_alu_imm := true.B;
switch(funct3) switch(funct3) {
{
// Type I // Type I
is(Funct3.ADD) is(Funct3.ADD)
{ {
@@ -298,5 +286,3 @@ class ControlUnit() extends Module {
} }
} }
} }