Moves control unit ops to separate files

src/main/scala/projet/op/OpLoad.scala

@@ -0,0 +1,59 @@
+package projet.op
+
+import chisel3._
+import chisel3.util.switch
+import projet.CUInterface
+import projet.AluOpCode
+import chisel3.util.is
+import projet.DMemSize
+
+object OpLoad {
+    // Implements functions for all instruction of the OpLoad kind
+    def opLoad(io: CUInterface) = {
+        val funct3 = io.instruction(14, 12);
+
+        // Meaning of Funct3 in the context of an OpLoad instruction
+        object Funct3 extends ChiselEnum {
+            val LB = "b000".U
+            val LH = "b001".U
+            val LW = "b010".U
+            val LBU = "b100".U
+            val LHU = "b101".U
+        }
+
+        io.alu_opcode := AluOpCode.Add
+        io.mux_alu_imm := true.B
+        io.mux_rega_pc := true.B
+        io.mux_regb_imm := false.B
+        io.mux_writeback_pc := true.B;
+        io.mux_executeout_dout := false.B;
+        io.reg_file_we := true.B
+        io.memory_en := true.B
+        io.memory_we := false.B
+        switch(funct3) {
+            // Byte load
+            is(Funct3.LB) {
+                io.memory_size := DMemSize.Byte
+                io.memory_sign_extend := true.B;
+            }
+            is(Funct3.LBU) {
+                io.memory_size := DMemSize.Byte
+            }
+
+            // Half load
+            is(Funct3.LH) {
+                io.memory_size := DMemSize.Half
+                io.memory_sign_extend := true.B;
+            }
+            is(Funct3.LHU) {
+                io.memory_size := DMemSize.Half
+            }
+
+            // Word load
+            is(Funct3.LW) {
+                io.memory_size := DMemSize.Word
+            }
+        }
+    }
+
+}