Moves control unit ops to separate files
This commit is contained in:
@@ -3,6 +3,12 @@ package projet
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import chisel3._
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import chisel3.util.switch
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import chisel3.util.is
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import projet.op.OpImm
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import projet.op.OpR
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import projet.op.OpBranch
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import projet.op.OpStore
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import projet.op.OpLoad
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import projet.op.OpImmW
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class CUInterface extends Bundle {
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val instruction = Input(UInt(32.W))
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@@ -57,7 +63,13 @@ class CUInterface extends Bundle {
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}
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object OpType extends ChiselEnum {
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val U, I, IR, J, B, S = Value
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val U, I, J, B, S = Value
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// Type IR is not defined in the RiscV specification
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// but the immediate needs to be handled differently
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// since the 31st bit indicates wether it is an
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// arithmetic or logical shift
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val IR = Value
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}
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object OpCode extends ChiselEnum {
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@@ -148,13 +160,13 @@ class ControlUnit() extends Module {
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// OpImm instructions
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is(OpCode.OpImm) {
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io.reg_file_we := true.B // Write to regfile
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opImm(funct3, funct7, io);
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OpImm.opImm(io)
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}
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// OpR instructions
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is(OpCode.OpR) {
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io.reg_file_we := true.B // Write to regfile
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opR(funct3, funct7, io);
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OpR.opR(io);
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}
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// J instructions
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@@ -191,368 +203,23 @@ class ControlUnit() extends Module {
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is(OpCode.OpBranch) {
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io.optype := OpType.B;
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opBranch(funct3, io);
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OpBranch.opBranch(io);
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}
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is(OpCode.OpStore) {
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io.optype := OpType.S
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opStore(funct3, io);
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OpStore.opStore(io);
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}
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is(OpCode.OpLoad) {
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io.optype := OpType.I
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opLoad(funct3, io);
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OpLoad.opLoad(io);
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}
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is(OpCode.OpImmW) {
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io.reg_file_we := true.B // Write to regfile
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io.optype := OpType.I
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opImmW(funct3, funct7, io);
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}
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}
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// Implements functions for all instruction of the opImm kind
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def opImm(funct3: UInt, funct7: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpImm instruction
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object Funct3 extends ChiselEnum {
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// Type I
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val ADDI = "b000".U
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val SLTI = "b010".U
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val SLTIU = "b011".U
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val XORI = "b100".U
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val ORI = "b110".U
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val ANDI = "b111".U
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// Type IR
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val SLLI = "b001".U
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val SRLI_SRAI = "b101".U // Right shifts
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}
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// Meaning of Funct7 in the context of SHIFTR IR instructions
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object IRFunct7 extends ChiselEnum {
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val SRLI = "b0000000".U
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val SRAI = "b0100000".U
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}
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io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
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io.mux_alu_imm := true.B;
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io.mux_rega_pc := true.B;
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io.alu_word_mode := false.B;
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switch(funct3) {
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// Type I
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is(Funct3.ADDI) {
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io.alu_opcode := AluOpCode.Add
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io.optype := OpType.I
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}
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is(Funct3.ANDI) {
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io.alu_opcode := AluOpCode.And
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io.optype := OpType.I
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}
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is(Funct3.ORI) {
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io.alu_opcode := AluOpCode.Or
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io.optype := OpType.I
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}
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is(Funct3.XORI) {
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io.alu_opcode := AluOpCode.Xor
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io.optype := OpType.I
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}
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is(Funct3.SLLI) {
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io.alu_opcode := AluOpCode.ShiftLeft
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io.optype := OpType.I
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}
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is(Funct3.SLTI) {
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io.alu_opcode := AluOpCode.LessThanSigned
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io.optype := OpType.I
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}
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is(Funct3.SLTIU) {
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io.alu_opcode := AluOpCode.LessThanUnsigned
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io.optype := OpType.I
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}
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// Type IR
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is(Funct3.SRLI_SRAI) {
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io.optype := OpType.IR
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switch(funct7) {
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is(IRFunct7.SRLI) {
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io.alu_opcode := AluOpCode.ShiftRight
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}
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is(IRFunct7.SRAI) {
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io.alu_opcode := AluOpCode.ShiftArithmeticRight
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}
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}
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}
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}
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}
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// Implements functions for all instruction of the opR kind
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def opR(funct3: UInt, funct7: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpR instruction
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object Funct3 extends ChiselEnum {
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// Type I
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val ADD_SUB = "b000".U
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val AND = "b111".U
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val OR = "b110".U
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val XOR = "b100".U
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val SLL = "b001".U
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val SLT = "b010".U
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val SLTU = "b011".U
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// Arithmetic op (discriminate by Funct7)
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val SRL_SRA = "b101".U
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}
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// Meaning of Funct7 in the context of SHIFTR IR instructions
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object IRFunct7 extends ChiselEnum {
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val SRL = "b0000000".U
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val SRA = "b0100000".U
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}
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object ADDFunct7 extends ChiselEnum {
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val ADD = "b0000000".U
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val SUB = "b0100000".U
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}
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io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
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io.mux_rega_pc := true.B;
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io.mux_alu_imm := true.B;
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switch(funct3) {
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// Type I
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is(Funct3.ADD_SUB) {
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switch(funct7) {
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is(ADDFunct7.ADD) {
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io.alu_opcode := AluOpCode.Add
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}
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is(ADDFunct7.SUB) {
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io.alu_opcode := AluOpCode.Sub
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}
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}
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}
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is(Funct3.AND) {
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io.alu_opcode := AluOpCode.And
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}
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is(Funct3.OR) {
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io.alu_opcode := AluOpCode.Or
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}
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is(Funct3.XOR) {
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io.alu_opcode := AluOpCode.Xor
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}
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is(Funct3.SLL) {
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io.alu_opcode := AluOpCode.ShiftLeft
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}
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is(Funct3.SLT) {
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io.alu_opcode := AluOpCode.LessThanSigned
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}
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is(Funct3.SLTU) {
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io.alu_opcode := AluOpCode.LessThanUnsigned
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}
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// Type IR
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is(Funct3.SRL_SRA) {
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switch(funct7) {
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is(IRFunct7.SRL) {
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io.alu_opcode := AluOpCode.ShiftRight
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}
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is(IRFunct7.SRA) {
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io.alu_opcode := AluOpCode.ShiftArithmeticRight
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}
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}
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}
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}
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}
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// Implements functions for all instruction of the branch kind
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def opBranch(funct3: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpBranch instruction
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object Funct3 extends ChiselEnum {
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val BEQ = "b000".U
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val BNE = "b001".U
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val BLT = "b100".U
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val BGE = "b101".U
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val BLTU = "b110".U
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val BGEU = "b111".U
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}
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val branch = WireInit(false.B);
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switch(funct3) {
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is(Funct3.BEQ) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.Equal
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := io.alu_comp_result
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}
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is(Funct3.BNE) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.Equal
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := ~io.alu_comp_result
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}
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// Signed comparison
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is(Funct3.BLT) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.LessThanSigned
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := io.alu_comp_result
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}
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is(Funct3.BGE) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.LessThanSigned
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := ~io.alu_comp_result
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}
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// Signed comparison
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is(Funct3.BLTU) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.LessThanUnsigned
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := io.alu_comp_result
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}
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is(Funct3.BGEU) {
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// Send operands from registers to alu
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io.alu_opcode := AluOpCode.LessThanUnsigned
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io.mux_rega_pc := true.B;
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io.mux_regb_imm := true.B;
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branch := ~io.alu_comp_result
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}
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}
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// Branch if comparison is successful
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when(branch) {
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io.mux_pcadder_writeback := true.B;
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io.mux_incrpc4_imm := false.B;
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io.mux_regpc_executepc := false.B;
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io.is_jump := true.B;
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}
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}
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// Implements functions for all instruction of the OpStore kind
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def opStore(funct3: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpStore instruction
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object Funct3 extends ChiselEnum {
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val SB = "b000".U
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val SH = "b001".U
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val SW = "b010".U
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}
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io.alu_opcode := AluOpCode.Add
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io.mux_alu_imm := true.B
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io.mux_rega_pc := true.B
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io.mux_regb_imm := false.B
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io.memory_we := true.B
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io.memory_en := true.B
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switch(funct3) {
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is(Funct3.SB) {
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io.memory_size := DMemSize.Byte
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}
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is(Funct3.SH) {
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io.memory_size := DMemSize.Half
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}
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is(Funct3.SW) {
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io.memory_size := DMemSize.Word
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}
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}
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}
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// Implements functions for all instruction of the OpLoad kind
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def opLoad(funct3: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpLoad instruction
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object Funct3 extends ChiselEnum {
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val LB = "b000".U
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val LH = "b001".U
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val LW = "b010".U
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val LBU = "b100".U
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val LHU = "b101".U
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}
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io.alu_opcode := AluOpCode.Add
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io.mux_alu_imm := true.B
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io.mux_rega_pc := true.B
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io.mux_regb_imm := false.B
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io.mux_writeback_pc := true.B;
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io.mux_executeout_dout := false.B;
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io.reg_file_we := true.B
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io.memory_en := true.B
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io.memory_we := false.B
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switch(funct3) {
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// Byte load
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is(Funct3.LB) {
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io.memory_size := DMemSize.Byte
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io.memory_sign_extend := true.B;
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}
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is(Funct3.LBU) {
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io.memory_size := DMemSize.Byte
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}
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// Half load
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is(Funct3.LH) {
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io.memory_size := DMemSize.Half
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io.memory_sign_extend := true.B;
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}
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is(Funct3.LHU) {
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io.memory_size := DMemSize.Half
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}
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// Word load
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is(Funct3.LW) {
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io.memory_size := DMemSize.Word
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}
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}
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}
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// ~~~ EXTENSIONS ~~~
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// ~~ Rv64i ~~
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// Implements functions for all instruction of the opImm, w kind
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def opImmW(funct3: UInt, funct7: UInt, io: CUInterface) = {
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// Meaning of Funct3 in the context of an OpImm instruction
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val _ = funct7;
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object Funct3 extends ChiselEnum {
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// Type I
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val ADDIW = "b000".U
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val SLLIW = "b001".U
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// Unimplemented
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val SRLIW_SRAIW = "b101".U // Right shifts
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}
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// Meaning of Funct7 in the context of SHIFTR IR instructions
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// object IRFunct7 extends ChiselEnum {
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// val SRLI = "b0000000".U
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// val SRAI = "b0100000".U
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// }
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io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
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io.mux_alu_imm := true.B;
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io.mux_rega_pc := true.B;
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switch(funct3) {
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// Type I
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is(Funct3.ADDIW) {
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io.alu_word_mode := true.B
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io.alu_opcode := AluOpCode.Add
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io.optype := OpType.I
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}
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OpImmW.opImmW(io);
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}
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}
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}
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Reference in New Issue
Block a user