Adds extension M instructions: not tested

src/main/scala/projet/ControlUnit.scala

@@ -78,9 +78,12 @@ object OpCode extends ChiselEnum {
     // Perfomrs some operation with rs1 and rd2
     // and writes back to a register
 
-    // add, and, or, xor, sll, srl, sra, slt, stlu
+    // add, and, or, xor, sll, srl, sra, slt, stlu, mul, mulh, mulhsu, mulhu, div, divu, rem, remu
     val OpR = "b0110011".U;
 
+    // mulw, divw, remw
+    val OpMw = "b0111011".U;
+
     // Type J
     val JAL = "b1101111".U
 
@@ -150,6 +153,12 @@ class ControlUnit() extends Module {
             opR(funct3, funct7, io);
         }
 
+        // OpMw instructions
+        is(OpCode.OpMw) {
+            io.reg_file_we := true.B // Write to regfile
+            opMw(funct3, io);
+        }
+
         // J instructions
         is(OpCode.JAL) {
             io.alu_opcode := AluOpCode.Add // ALU is unused
@@ -305,7 +314,7 @@ class ControlUnit() extends Module {
             val SUB = "b0100000".U
         }
 
-        io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
+        io.mux_regb_imm := true.B;
         io.mux_rega_pc := true.B;
         io.mux_alu_imm := true.B;
         switch(funct3) {
@@ -358,6 +367,12 @@ class ControlUnit() extends Module {
                 }
             }
         }
+
+        // Switch to mul extension
+        val RV32M_FUNCT7 = "b0000001".U
+        when(funct7 === RV32M_FUNCT7) {
+            opM(funct3, io);
+        }
     }
 
     // Implements functions for all instruction of the branch kind
@@ -505,4 +520,74 @@ class ControlUnit() extends Module {
             }
         }
     }
+    // Implements functions for instructions of the M extension of type R
+    def opM(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpM instruction
+        object Funct3 extends ChiselEnum {
+            val MUL = "b000".U
+            val MULH = "b001".U
+            val MULHSU = "b010".U
+            val MULHU = "b011".U
+            val DIV = "b100".U
+            val DIVU = "b101".U
+            val REM = "b110".U
+            val REMU = "b111".U
+        }
+
+        switch(funct3) {
+            is(Funct3.MUL) {
+                io.alu_opcode := AluOpCode.Mul
+            }
+            is(Funct3.MULH) {
+                io.alu_opcode := AluOpCode.Mulh
+            }
+            is(Funct3.MULHSU) {
+                io.alu_opcode := AluOpCode.Mulhsu
+            }
+            is(Funct3.MULHU) {
+                io.alu_opcode := AluOpCode.Mulhu
+            }
+            is(Funct3.DIV) {
+                io.alu_opcode := AluOpCode.Div
+            }
+            is(Funct3.DIVU) {
+                io.alu_opcode := AluOpCode.Divu
+            }
+            is(Funct3.REM) {
+                io.alu_opcode := AluOpCode.Rem
+            }
+            is(Funct3.REMU) {
+                io.alu_opcode := AluOpCode.Remu
+            }
+        }
+    }
+    // Implements functions for instructions of the M extension with word size
+    def opMw(funct3: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpMw instruction
+        object Funct3 extends ChiselEnum {
+            val MULW = "b000".U
+            val DIVW = "b100".U
+            val DIVUW = "b101".U
+            val REMW = "b110".U
+            val REMUW = "b111".U
+        }
+
+        switch(funct3) {
+            is(Funct3.MULW) {
+                io.alu_opcode := AluOpCode.Mulw
+            }
+            is(Funct3.DIVW) {
+                io.alu_opcode := AluOpCode.Divw
+            }
+            is(Funct3.DIVUW) {
+                io.alu_opcode := AluOpCode.Divuw
+            }
+            is(Funct3.REMW) {
+                io.alu_opcode := AluOpCode.Remw
+            }
+            is(Funct3.REMUW) {
+                io.alu_opcode := AluOpCode.Remuw
+            }
+        }
+    }
 }