diff --git a/src/main/scala/projet/ControlUnit.scala b/src/main/scala/projet/ControlUnit.scala
index f9d984d..a948783 100644
--- a/src/main/scala/projet/ControlUnit.scala
+++ b/src/main/scala/projet/ControlUnit.scala
@@ -142,8 +142,9 @@ class ControlUnit() extends Module {
     val funct7 = io.instruction(31, 25);
 
     switch(opcode) {
+        // ~~~ Single instruction OpCodes ~~
 
-        // U instructions
+        // ~ U instructions ~
         is(OpCode.LUI) {
             io.reg_file_we := true.B // Write to regfile
             io.mux_alu_imm := false.B // Send immy directly to refile
@@ -157,19 +158,7 @@ class ControlUnit() extends Module {
             io.optype := OpType.U
         }
 
-        // OpImm instructions
-        is(OpCode.OpImm) {
-            io.reg_file_we := true.B // Write to regfile
-            OpImm.opImm(io)
-        }
-
-        // OpR instructions
-        is(OpCode.OpR) {
-            io.reg_file_we := true.B // Write to regfile
-            OpR.opR(io);
-        }
-
-        // J instructions
+        // ~ J instructions ~
         is(OpCode.JAL) {
             io.alu_opcode := AluOpCode.Add // ALU is unused
 
@@ -201,24 +190,27 @@ class ControlUnit() extends Module {
             io.optype := OpType.I
         }
 
+        is(OpCode.OpImm) {
+            OpImm.opImm(io)
+        }
+
+        is(OpCode.OpR) {
+            OpR.opR(io);
+        }
+
         is(OpCode.OpBranch) {
-            io.optype := OpType.B;
             OpBranch.opBranch(io);
         }
 
         is(OpCode.OpStore) {
-            io.optype := OpType.S
             OpStore.opStore(io);
         }
 
         is(OpCode.OpLoad) {
-            io.optype := OpType.I
             OpLoad.opLoad(io);
         }
 
         is(OpCode.OpImmW) {
-            io.reg_file_we := true.B // Write to regfile
-            io.optype := OpType.I
             OpImmW.opImmW(io);
         }
     }
diff --git a/src/main/scala/projet/op/OpBranch.scala b/src/main/scala/projet/op/OpBranch.scala
index 0653ac9..e858e5e 100644
--- a/src/main/scala/projet/op/OpBranch.scala
+++ b/src/main/scala/projet/op/OpBranch.scala
@@ -5,6 +5,7 @@ import chisel3.util.switch
 import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
+import projet.OpType
 
 object OpBranch {
 // Implements functions for all instruction of the branch kind
@@ -21,6 +22,7 @@ object OpBranch {
             val BGEU = "b111".U
         }
 
+        io.optype := OpType.B
         val branch = WireInit(false.B);
         switch(funct3) {
             is(Funct3.BEQ) {
diff --git a/src/main/scala/projet/op/OpImm.scala b/src/main/scala/projet/op/OpImm.scala
index 6c1f75f..5edcd44 100644
--- a/src/main/scala/projet/op/OpImm.scala
+++ b/src/main/scala/projet/op/OpImm.scala
@@ -30,6 +30,7 @@ object OpImm {
             val ShiftRight = "b101".U
         }
 
+        io.reg_file_we := true.B // Write to regfile
         io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_alu_imm := true.B;
         io.mux_rega_pc := true.B;
diff --git a/src/main/scala/projet/op/OpImmW.scala b/src/main/scala/projet/op/OpImmW.scala
index d885713..0a1463a 100644
--- a/src/main/scala/projet/op/OpImmW.scala
+++ b/src/main/scala/projet/op/OpImmW.scala
@@ -21,6 +21,8 @@ object OpImmW {
             val SRLIW_SRAIW = "b101".U // Right shifts
         }
 
+        io.optype := OpType.I;
+        io.reg_file_we := true.B // Write to regfile
         io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_alu_imm := true.B;
         io.mux_rega_pc := true.B;
diff --git a/src/main/scala/projet/op/OpLoad.scala b/src/main/scala/projet/op/OpLoad.scala
index c387aa1..7e61b66 100644
--- a/src/main/scala/projet/op/OpLoad.scala
+++ b/src/main/scala/projet/op/OpLoad.scala
@@ -6,6 +6,7 @@ import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
 import projet.DMemSize
+import projet.OpType
 
 object OpLoad {
     // Implements functions for all instruction of the OpLoad kind
@@ -21,6 +22,7 @@ object OpLoad {
             val LHU = "b101".U
         }
 
+        io.optype := OpType.I
         io.alu_opcode := AluOpCode.Add
         io.mux_alu_imm := true.B
         io.mux_rega_pc := true.B
diff --git a/src/main/scala/projet/op/OpR.scala b/src/main/scala/projet/op/OpR.scala
index e66b519..740da98 100644
--- a/src/main/scala/projet/op/OpR.scala
+++ b/src/main/scala/projet/op/OpR.scala
@@ -5,6 +5,7 @@ import chisel3.util.switch
 import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
+import projet.OpType
 
 object OpR {
     // implements functions for all instruction of the opr kind
@@ -37,6 +38,7 @@ object OpR {
             val SUB = "b0100000".U
         }
 
+        io.reg_file_we := true.B // Write to regfile
         io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_rega_pc := true.B;
         io.mux_alu_imm := true.B;
diff --git a/src/main/scala/projet/op/OpStore.scala b/src/main/scala/projet/op/OpStore.scala
index f48d1ba..5b69ec5 100644
--- a/src/main/scala/projet/op/OpStore.scala
+++ b/src/main/scala/projet/op/OpStore.scala
@@ -6,6 +6,7 @@ import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
 import projet.DMemSize
+import projet.OpType
 
 object OpStore {
     // Implements functions for all instruction of the OpStore kind
@@ -19,6 +20,7 @@ object OpStore {
             val SW = "b010".U
         }
 
+        io.optype := OpType.S
         io.alu_opcode := AluOpCode.Add
         io.mux_alu_imm := true.B
         io.mux_rega_pc := true.B