Starts adding rust in the toolchain

Makefile

@@ -67,7 +67,11 @@ compile: $(MEM)
 $(MEM_DIR):
 	@mkdir -p $@/tests/op
 	@mkdir -p $@/programs
+	@mkdir -p $@/programs_rust
 
+$(MEM_DIR)/programs_rust/%.elf: bench/programs_rust/% |$(MEM_DIR)
+	cd bench/programs_rust && cargo build --release --bin=$(basename $(notdir $@))
+	cp -f bench/programs_rust/target/riscv64i/release/$(basename $(notdir $@)) $@
 $(MEM_DIR)/crt.o: $(BENCH_DIR)/crt.S |$(MEM_DIR)
 	$(CC) $(CFLAGS) -c $< -o $@
 $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o |$(MEM_DIR)
@@ -106,14 +110,16 @@ mill:
 
 autotest: mill test-bench/mem/tests/$(PROG).mem ##! Lance la simulation automatique pour tous les tests ou juste celui fourni dans PROG
 
-testall: mill compile
+testall: mill compile ##! Lance la simulation automatique pour tous les tests en parallèle
-	@# Limite le nombre de processeurs et la ram utilisée pour les tests parellèle
+	@# Limite le nombre de processeurs et la ram utilisée pour les tests parallèle
 	@( \
 		ulimit -v $(TEST_MAX_RAM); \
 		PROOT=$(PWD) taskset -c 0-$(TEST_MAX_PROCS) ./mill TPchisel.test.testOnly $(TOP_REP).ZzTopAllSpec \
 	)
 
-simulation: mill compile ##! Lance gtkwave sur le test fourni dans PROG
+$(PROG): $(MEM_DIR)/$(PROG).mem
+
+simulation: mill $(PROG) ##! Lance gtkwave sur le test fourni dans PROG
 	@$(call check_vars,PROG)
 	@PROOT=$(PWD) PROG=$(PROG) CYCLES=$(CYCLES) ./mill TPchisel.test.testOnly $(TOP_REP).$(TOP_TEST) -- -DemitVcd=1 -z "gtkwave"
 	@gtkwave -a common/config.gtkw ./build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd

bench/programs_rust/.cargo/config.toml

@@ -0,0 +1,14 @@
+[build]
+target = "riscv64i.json"
+
+[target.riscv64i]
+linker = "riscv64-unknown-elf-ld"
+# linker = "rust-lld"
+
+rustflags = [
+    # "-C", "link-arg=-nostartfiles",
+    "-C", "link-arg=-T../link.ld",
+]
+
+[unstable]
+build-std = ["core", "compiler_builtins"]

bench/programs_rust/.gitignore

@@ -0,0 +1,3 @@
+.helix/
+target/
+Cargo.lock

bench/programs_rust/Cargo.toml

@@ -0,0 +1,13 @@
+[workspace]
+resolver = "3"
+members = ["fpga_lib", "hello_rust"]
+
+[profile.release]
+panic = "abort"
+codegen-units = 1 # better optimizations
+lto = true # better optimizations
+strip = true
+opt-level = "z"
+
+[profile.dev]
+panic = "abort"

bench/programs_rust/fpga_lib/Cargo.toml

@@ -0,0 +1,6 @@
+[package]
+name = "fpga_lib"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]

bench/programs_rust/fpga_lib/src/lib.rs

@@ -0,0 +1,11 @@
+#![no_std]
+
+#[macro_export]
+macro_rules! panic_handler {
+    () => {
+        #[panic_handler]
+        fn panic(_info: &core::panic::PanicInfo) -> ! {
+            loop {}
+        }
+    };
+}

bench/programs_rust/hello_rust/Cargo.toml

@@ -0,0 +1,7 @@
+[package]
+name = "hello_rust"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+fpga_lib = { path = "../fpga_lib" }

bench/programs_rust/hello_rust/src/main.rs

@@ -0,0 +1,18 @@
+#![no_std]
+#![no_main]
+
+use core::arch::asm;
+
+use fpga_lib::panic_handler;
+
+panic_handler! {}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _start() -> ! {
+    unsafe {
+        asm! {
+            "li x31, 0xdead0"
+        }
+    }
+    loop {}
+}

bench/programs_rust/riscv64i.json

@@ -0,0 +1,21 @@
+{
+    "llvm-target": "riscv64",
+    "llvm-abiname": "lp64",
+    "abi": "lp64",
+    "data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
+    "target-endian": "little",
+    "target-pointer-width": 64,
+    "arch": "riscv64",
+    "os": "none",
+    "vendor": "unknown",
+    "env": "",
+    "features": "+i",
+    "linker-flavor": "ld.lld",
+    "linker": "riscv64-unknown-elf-ld",
+    "executables": true,
+    "panic-strategy": "abort",
+    "relocation-model": "static",
+    "disable-redzone": true,
+    "emit-debug-gdb-scripts": false,
+    "eh-frame-header": false
+}

bench/programs_rust/rust-toolchain.toml

@@ -0,0 +1,2 @@
+[toolchain]
+channel = "nightly"

src/main/scala/projet/op/OpRW.scala

@@ -5,7 +5,6 @@ import chisel3.util.switch
 import projet.CUInterface
 import projet.AluOpCode
 import chisel3.util.is
-import projet.OpType
 
 object OpRW {
     // Implements functions for all instruction of the opImm, w  kind