Merge branch 'rv64i' into rv64im

bench/tests/op/addiw.s

@@ -0,0 +1,14 @@
+# expected: 0000000000000000, FFFFFFFFFFFFFFFF, 0000000000000010
+    .text
+_start:
+    # This test CANNOT use li as it uses addiw under the hood
+
+    # 0 addition
+    addiw x31, x0, 0
+
+    # all bits addition + sign extension to 32 bits then 64 bits
+    addiw x31, x0, (-1)
+
+    # simple addition
+    addi x1, x0, 8
+    addiw x31, x1, 8

bench/tests/op/li.s

@@ -0,0 +1,9 @@
+# exepected: 1234567890ABCDEF, 00000000FFFFFFFF
+
+# li is a PSEUDO-INSTRUCTION.
+# This test makes sure we can reliably load 64bit words
+# into the processor as it is essential for all other tests
+    .text
+_start:
+    li x31, 0x1234567890ABCDEF
+    li x31, 0x00000000FFFFFFFF