Stage 1 + removes hardcoded paths

.vscode/settings.json

@@ -0,0 +1,5 @@
+{
+    "files.watcherExclude": {
+        "**/target": true
+    }
+}

Makefile

@@ -66,7 +66,7 @@ $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o|$(MEM_DIR)
 $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.s |$(MEM_DIR)
 	$(CC) $(CFLAGS) -o $@ $<
 $(MEM_DIR)/%.mem: $(MEM_DIR)/%.elf |$(MEM_DIR) 
-	$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk
+	$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk > $@
 
 
 ###############################################################################

common/config.gtkw

@@ -21,7 +21,7 @@
 @200
 -Instruction
 @c04023
-^>1 /matieres/3MMFMN/riscv32/bin/spike-dasm
+^>1 spike-dasm
 TOP.svsimTestbench.dut.core.insn[31:0]
 @29
 (0)TOP.svsimTestbench.dut.core.insn[31:0]

src/main/scala/projet/Rv32i.scala

@@ -10,5 +10,35 @@ class Rv32i(sim: Boolean = true) extends Module {
     val valid_x31  = if (sim)  Some(Output(Bool())) else None
   })
 
-  locally(sim)
+  val reg_pc = RegInit(0.U(32.W));
+  
+  // Increment PC each clock
+  reg_pc := reg_pc + 4.U;
+
+  // Read instruction
+  io.ibus.en := true.B;
+  io.ibus.addr := reg_pc;
+
+  val insn = io.ibus.rdata;
+  dontTouch(insn);
+
+  // Debug instruction
+  io.x31 := insn;
+  if(sim)
+  {
+    io.valid_x31.get := true.B;
+  }
+
+  //io.ibus.wdata
+  //io.ibus.be
+
+  io.dbus.addr := 0.U;
+  io.dbus.wdata := 0.U;
+  io.dbus.be := VecInit(false.B,false.B,false.B,false.B)
+  io.dbus.en := false.B;
+
+  io.ibus.wdata := 0.U;
+  io.ibus.be := VecInit(false.B,false.B,false.B,false.B)
+
+  //locally(sim)
 }