Stage 1 + removes hardcoded paths

src/main/scala/projet/Rv32i.scala

@@ -10,5 +10,35 @@ class Rv32i(sim: Boolean = true) extends Module {
     val valid_x31  = if (sim)  Some(Output(Bool())) else None
   })
 
-  locally(sim)
+  val reg_pc = RegInit(0.U(32.W));
+  
+  // Increment PC each clock
+  reg_pc := reg_pc + 4.U;
+
+  // Read instruction
+  io.ibus.en := true.B;
+  io.ibus.addr := reg_pc;
+
+  val insn = io.ibus.rdata;
+  dontTouch(insn);
+
+  // Debug instruction
+  io.x31 := insn;
+  if(sim)
+  {
+    io.valid_x31.get := true.B;
+  }
+
+  //io.ibus.wdata
+  //io.ibus.be
+
+  io.dbus.addr := 0.U;
+  io.dbus.wdata := 0.U;
+  io.dbus.be := VecInit(false.B,false.B,false.B,false.B)
+  io.dbus.en := false.B;
+
+  io.ibus.wdata := 0.U;
+  io.ibus.be := VecInit(false.B,false.B,false.B,false.B)
+
+  //locally(sim)
 }