Merge branch 'main' into rv64im

src/test/scala/projet/ZzTopCommon.scala

@@ -7,11 +7,12 @@ import chisel3.simulator.scalatest.ChiselSim
 
 object ZzTopCommon extends AnyFreeSpec with ChiselSim {
     def expectedValuesFromAsm(path: String): Seq[BigInt] = {
-        val line =
-            Source.fromFile(path).getLines().find(_.startsWith("# expected:"))
-        line match {
-            case Some(l) =>
-                l.stripPrefix("# expected:")
+        Source
+            .fromFile(path)
+            .getLines()
+            .filter(_.startsWith("# expected:"))
+            .map(
+                _.stripPrefix("# expected:")
                     .split(",")
                     .map(_.trim)
                     .filter(_.nonEmpty)
@@ -24,9 +25,10 @@ object ZzTopCommon extends AnyFreeSpec with ChiselSim {
                         }
                     })
                     .toSeq
-            case None =>
-                Seq.empty
-        }
+            )
+            .fold(Seq.empty)((acc, line) => {
+                acc.concat(line)
+            })
     }
 
     def failTrace(msg: String = "Erreur", trace: ListBuffer[String]): Unit = {