Merge branch 'main' into rv64im

src/main/scala/projet/Alu.scala

@@ -49,11 +49,11 @@ class Alu extends Module {
 
     switch(io.opcode) {
         is(Add) {
-            out := io.a + io.b;
+            out := op_a + op_b;
         }
 
         is(Sub) {
-            out := io.a - io.b;
+            out := op_a - op_b;
         }
 
         is(Mul) {
@@ -109,56 +109,61 @@ class Alu extends Module {
         }
 
         is(And) {
-            out := io.a & io.b;
+            out := op_a & op_b;
         }
 
         is(Or) {
-            out := io.a | io.b;
+            out := op_a | op_b;
         }
 
         is(Xor) {
-            out := io.a ^ io.b;
+            out := op_a ^ op_b;
         }
 
         is(ShiftLeft) {
-            out := io.a << io.b(5, 0);
+            out := op_a << op_b(5, 0);
         }
 
         is(ShiftRight) {
-            out := io.a >> io.b(5, 0);
+            out := op_a >> op_b(5, 0);
         }
 
         is(ShiftArithmeticRight) {
             // >> means arithmetic shift for SInts
-            out := (io.a.asSInt >> io.b(5, 0)).asUInt;
+            out := (op_a.asSInt >> op_b(5, 0)).asUInt;
+            // Signed shift on 32bit requires careful handling
+            when(io.word_mode) {
+
+                out := (op_a(31, 0).asSInt >> op_b(5, 0)).asUInt
+            }
         }
 
         is(LessThanUnsigned) {
-            val less_than = io.a < io.b;
+            val less_than = op_a < op_b;
             out := less_than;
             io.comp_result := less_than;
         }
 
         is(LessThanSigned) {
-            val less_than = io.a.asSInt < io.b.asSInt
+            val less_than = op_a.asSInt < op_b.asSInt
             out := less_than
             io.comp_result := less_than;
         }
 
         is(GreaterEqualUnsigned) {
-            val geq_than = io.a >= io.b;
+            val geq_than = op_a >= op_b;
             out := geq_than
             io.comp_result := geq_than;
         }
 
         is(GreaterEqualSigned) {
-            val geq_than = io.a.asSInt >= io.b.asSInt
+            val geq_than = op_a.asSInt >= op_b.asSInt
             out := geq_than
             io.comp_result := geq_than;
         }
 
         is(Equal) {
-            io.comp_result := io.a === io.b;
+            io.comp_result := op_a === op_b;
         }
     }