Merge branch 'main' into rv64im

src/main/scala/projet/Alu.scala

@@ -49,11 +49,11 @@ class Alu extends Module {
 
     switch(io.opcode) {
         is(Add) {
-            out := io.a + io.b;
+            out := op_a + op_b;
         }
 
         is(Sub) {
-            out := io.a - io.b;
+            out := op_a - op_b;
         }
 
         is(Mul) {
@@ -109,56 +109,61 @@ class Alu extends Module {
         }
 
         is(And) {
-            out := io.a & io.b;
+            out := op_a & op_b;
         }
 
         is(Or) {
-            out := io.a | io.b;
+            out := op_a | op_b;
         }
 
         is(Xor) {
-            out := io.a ^ io.b;
+            out := op_a ^ op_b;
         }
 
         is(ShiftLeft) {
-            out := io.a << io.b(5, 0);
+            out := op_a << op_b(5, 0);
         }
 
         is(ShiftRight) {
-            out := io.a >> io.b(5, 0);
+            out := op_a >> op_b(5, 0);
         }
 
         is(ShiftArithmeticRight) {
             // >> means arithmetic shift for SInts
-            out := (io.a.asSInt >> io.b(5, 0)).asUInt;
+            out := (op_a.asSInt >> op_b(5, 0)).asUInt;
+            // Signed shift on 32bit requires careful handling
+            when(io.word_mode) {
+
+                out := (op_a(31, 0).asSInt >> op_b(5, 0)).asUInt
+            }
         }
 
         is(LessThanUnsigned) {
-            val less_than = io.a < io.b;
+            val less_than = op_a < op_b;
             out := less_than;
             io.comp_result := less_than;
         }
 
         is(LessThanSigned) {
-            val less_than = io.a.asSInt < io.b.asSInt
+            val less_than = op_a.asSInt < op_b.asSInt
             out := less_than
             io.comp_result := less_than;
         }
 
         is(GreaterEqualUnsigned) {
-            val geq_than = io.a >= io.b;
+            val geq_than = op_a >= op_b;
             out := geq_than
             io.comp_result := geq_than;
         }
 
         is(GreaterEqualSigned) {
-            val geq_than = io.a.asSInt >= io.b.asSInt
+            val geq_than = op_a.asSInt >= op_b.asSInt
             out := geq_than
             io.comp_result := geq_than;
         }
 
         is(Equal) {
-            io.comp_result := io.a === io.b;
+            io.comp_result := op_a === op_b;
         }
     }
 

src/main/scala/projet/ControlUnit.scala

@@ -10,6 +10,7 @@ import projet.op.OpStore
 import projet.op.OpLoad
 import projet.op.OpImmW
 import projet.op.OpM
+import projet.op.OpRW
 
 class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
@@ -54,7 +55,7 @@ class CUInterface extends Bundle {
     val mux_regpc_executepc = Output(Bool())
 
     // Selects pc adder or write back for pc write
-    val mux_pcadder_writeback = Output(Bool())
+    val mux_pcadder_jalrwriteback = Output(Bool())
 
     // Selects pc or write back for register write
     val mux_writeback_pc = Output(Bool())
@@ -117,6 +118,9 @@ object OpCode extends ChiselEnum {
 
     // ~~ Rv64i ~~
     val OpImmW = "b0011011".U
+
+    // TypeR
+    val OpRW = "b0111011".U
 }
 
 class ControlUnit() extends Module {
@@ -137,7 +141,7 @@ class ControlUnit() extends Module {
     io.mux_incrpc4_imm := true.B;
     io.mux_regpc_executepc := true.B;
     io.mux_writeback_pc := true.B;
-    io.mux_pcadder_writeback := true.B;
+    io.mux_pcadder_jalrwriteback := true.B;
     io.mux_executeout_dout := true.B;
 
     // Decode instruction
@@ -175,7 +179,7 @@ class ControlUnit() extends Module {
             io.is_jump := true.B
             io.mux_incrpc4_imm := false.B; // Send the immediate in PC
             io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
-            io.mux_pcadder_writeback := true.B;
+            io.mux_pcadder_jalrwriteback := true.B;
             io.optype := OpType.J
         }
 
@@ -190,7 +194,7 @@ class ControlUnit() extends Module {
             io.mux_regb_imm := false.B; // Send imm to ALU B
 
             io.mux_alu_imm := true.B; // Send alu out to write back line
-            io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
+            io.mux_pcadder_jalrwriteback := false.B; // Set pc to writeback dest
             io.optype := OpType.I
         }
 
@@ -222,5 +226,9 @@ class ControlUnit() extends Module {
         is(OpCode.OpImmW) {
             OpImmW.opImmW(io);
         }
+
+        is(OpCode.OpRW) {
+            OpRW.opRW(io);
+        }
     }
 }

src/main/scala/projet/DMem.scala

@@ -80,7 +80,7 @@ class DMem extends Module {
     }
 
     // Data out is available one cycle after the read request
-    val read_addr = Delay.Delay(io.addr, 2, 0.U);
+    val read_addr = Delay.Delay(io.addr, 1, 0.U);
     val read_sign_extend = Delay.Delay(io.sign_extend, 1, false.B);
     when(Delay.Delay(io.en && !io.we, 1, false.B)) {
         switch(Delay.Delay(io.size, 1, DMemSize.Byte)) {

src/main/scala/projet/Rv64i.scala

@@ -119,6 +119,8 @@ class Rv64i(sim: Boolean = true) extends Module {
     // Select what to send on writeback line
     val execute_out = Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
     reg_execute_out := execute_out;
+    // Jalr line is directly the execute output
+    val jalr_line = execute_out
 
     reg_mux_executeout_dout := control_unit.io.mux_executeout_dout;
 
@@ -131,9 +133,9 @@ class Rv64i(sim: Boolean = true) extends Module {
 
     // Writeback pipelining registers
     reg_pc := Mux(
-        Delay.Delay(control_unit.io.mux_pcadder_writeback, 1, true.B),
+        control_unit.io.mux_pcadder_jalrwriteback,
         pc_adder_out,
-        writeback_line
+        jalr_line
     );
 
     dmem.io.data_in := rs2_data

src/main/scala/projet/op/OpBranch.scala

@@ -78,7 +78,7 @@ object OpBranch {
 
         // Branch if comparison is successful
         when(branch) {
-            io.mux_pcadder_writeback := true.B;
+            io.mux_pcadder_jalrwriteback := true.B;
             io.mux_incrpc4_imm := false.B;
             io.mux_regpc_executepc := false.B;
             io.is_jump := true.B;

src/main/scala/projet/op/OpImmW.scala

@@ -17,8 +17,7 @@ object OpImmW {
             val ADDIW = "b000".U
             val SLLIW = "b001".U
 
-            // Unimplemented
-            val SRLIW_SRAIW = "b101".U // Right shifts
+            val ShiftWordRight = "b101".U // Right shifts
         }
 
         io.optype := OpType.I;
@@ -26,13 +25,29 @@ object OpImmW {
         io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_alu_imm := true.B;
         io.mux_rega_pc := true.B;
+        io.alu_word_mode := true.B
         switch(funct3) {
             // Type I
             is(Funct3.ADDIW) {
-                io.alu_word_mode := true.B
                 io.alu_opcode := AluOpCode.Add
                 io.optype := OpType.I
             }
+
+            is(Funct3.SLLIW) {
+                io.alu_opcode := AluOpCode.ShiftLeft
+                io.optype := OpType.I
+            }
+
+            is(Funct3.ShiftWordRight) {
+                io.optype := OpType.IR
+
+                // Second-to-last bit indicates arithmetic or logical shift
+                when(io.instruction(30)) {
+                    io.alu_opcode := AluOpCode.ShiftArithmeticRight
+                }.otherwise {
+                    io.alu_opcode := AluOpCode.ShiftRight
+                }
+            }
         }
     }
 }

src/main/scala/projet/op/OpLoad.scala

@@ -15,11 +15,18 @@ object OpLoad {
 
         // Meaning of Funct3 in the context of an OpLoad instruction
         object Funct3 extends ChiselEnum {
+            // Zero extend
             val LB = "b000".U
             val LH = "b001".U
             val LW = "b010".U
+
+            // Sign extend
             val LBU = "b100".U
             val LHU = "b101".U
+            val LWU = "b110".U
+
+            // Arch width
+            val LD = "b011".U
         }
 
         io.optype := OpType.I
@@ -32,6 +39,7 @@ object OpLoad {
         io.reg_file_we := true.B
         io.memory_en := true.B
         io.memory_we := false.B
+        io.memory_sign_extend := false.B;
         switch(funct3) {
             // Byte load
             is(Funct3.LB) {
@@ -54,6 +62,15 @@ object OpLoad {
             // Word load
             is(Funct3.LW) {
                 io.memory_size := DMemSize.Word
+                io.memory_sign_extend := true.B;
+            }
+            is(Funct3.LWU) {
+                io.memory_size := DMemSize.Word
+            }
+
+            // Long load
+            is(Funct3.LD) {
+                io.memory_size := DMemSize.Long
             }
         }
     }

src/main/scala/projet/op/OpRW.scala

@@ -0,0 +1,70 @@
+package projet.op
+
+import chisel3._
+import chisel3.util.switch
+import projet.CUInterface
+import projet.AluOpCode
+import chisel3.util.is
+
+object OpRW {
+    // Implements functions for all instruction of the opImm, w  kind
+    def opRW(io: CUInterface) = {
+        val funct3 = io.instruction(14, 12);
+        val funct7 = io.instruction(31, 25);
+
+        // Meaning of Funct3 in the context of an OpImm instruction
+        object Funct3 extends ChiselEnum {
+            // Type I
+            val AdditionSubstraction = "b000".U
+            val SLLW = "b001".U
+            val ShiftRight = "b101".U
+
+            // Unimplemented
+            val ShiftWordRight = "b101".U // Right shifts
+        }
+
+        object AdditionSubstractionFunct7 extends ChiselEnum {
+            val ADDW = "b0000000".U
+            val SUBW = "b0100000".U
+        }
+
+        object ShiftWordRightFunct7 extends ChiselEnum {
+            val SRLW = "b0000000".U
+            val SRAW = "b0100000".U
+        }
+
+        io.reg_file_we := true.B // Write to regfile
+        io.alu_word_mode := true.B
+        io.mux_regb_imm := true.B; // OpImm are operations with imm, so send imm to ALU
+        io.mux_rega_pc := true.B;
+        io.mux_alu_imm := true.B;
+        switch(funct3) {
+            // Type I
+            is(Funct3.AdditionSubstraction) {
+                switch(funct7) {
+                    is(AdditionSubstractionFunct7.ADDW) {
+                        io.alu_opcode := AluOpCode.Add
+                    }
+                    is(AdditionSubstractionFunct7.SUBW) {
+                        io.alu_opcode := AluOpCode.Sub
+                    }
+                }
+            }
+
+            is(Funct3.SLLW) {
+                io.alu_opcode := AluOpCode.ShiftLeft
+            }
+
+            is(Funct3.ShiftWordRight) {
+                switch(funct7) {
+                    is(ShiftWordRightFunct7.SRAW) {
+                        io.alu_opcode := AluOpCode.ShiftArithmeticRight
+                    }
+                    is(ShiftWordRightFunct7.SRLW) {
+                        io.alu_opcode := AluOpCode.ShiftRight
+                    }
+                }
+            }
+        }
+    }
+}

src/main/scala/projet/op/OpStore.scala

@@ -18,6 +18,7 @@ object OpStore {
             val SB = "b000".U
             val SH = "b001".U
             val SW = "b010".U
+            val SD = "b011".U
         }
 
         io.optype := OpType.S
@@ -37,6 +38,9 @@ object OpStore {
             is(Funct3.SW) {
                 io.memory_size := DMemSize.Word
             }
+            is(Funct3.SD) {
+                io.memory_size := DMemSize.Long
+            }
         }
     }
 }